| Message ID | 20191005164212.3646-1-vidyas@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | [1/2] PCI: tegra: Fix CLKREQ dependency programming | expand |
On Sat, Oct 05, 2019 at 10:12:11PM +0530, Vidya Sagar wrote: > Corrects the programming to provide REFCLK to the downstream device > when there is no CLKREQ sideband signal routing present from root port > to the endpont. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > drivers/pci/controller/dwc/pcie-tegra194.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c > index f89f5acee72d..cbe95f0ea0ca 100644 > --- a/drivers/pci/controller/dwc/pcie-tegra194.c > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > @@ -40,8 +40,6 @@ > #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) > #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) > #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) > -#define APPL_PINMUX_CLKREQ_OUT_OVRD_EN BIT(9) > -#define APPL_PINMUX_CLKREQ_OUT_OVRD BIT(10) > > #define APPL_CTRL 0x4 > #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) > @@ -1193,8 +1191,8 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, > > if (!pcie->supports_clkreq) { > val = appl_readl(pcie, APPL_PINMUX); > - val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN; > - val |= APPL_PINMUX_CLKREQ_OUT_OVRD; > + val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN; > + val &= ~APPL_PINMUX_CLKREQ_OVERRIDE; > appl_writel(pcie, val, APPL_PINMUX); > } If we do support CLKREQ, do we have to explicitly set the OVERRIDE bit? Or clear the OVERRIDE_EN bit? Is it always guaranteed that the defaults (OVERRIDE_EN = 0) is applied at this point? That's an issue that's orthogonal to this patch, though, so for this one: Acked-by: Thierry Reding <treding@nvidia.com>
On Sat, Oct 05, 2019 at 10:12:11PM +0530, Vidya Sagar wrote: > Corrects the programming to provide REFCLK to the downstream device > when there is no CLKREQ sideband signal routing present from root port > to the endpont. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > drivers/pci/controller/dwc/pcie-tegra194.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) Applied to pci/tegra, thanks. Lorenzo > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c > index f89f5acee72d..cbe95f0ea0ca 100644 > --- a/drivers/pci/controller/dwc/pcie-tegra194.c > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > @@ -40,8 +40,6 @@ > #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) > #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) > #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) > -#define APPL_PINMUX_CLKREQ_OUT_OVRD_EN BIT(9) > -#define APPL_PINMUX_CLKREQ_OUT_OVRD BIT(10) > > #define APPL_CTRL 0x4 > #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) > @@ -1193,8 +1191,8 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, > > if (!pcie->supports_clkreq) { > val = appl_readl(pcie, APPL_PINMUX); > - val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN; > - val |= APPL_PINMUX_CLKREQ_OUT_OVRD; > + val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN; > + val &= ~APPL_PINMUX_CLKREQ_OVERRIDE; > appl_writel(pcie, val, APPL_PINMUX); > } > > -- > 2.17.1 >
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index f89f5acee72d..cbe95f0ea0ca 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -40,8 +40,6 @@ #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) -#define APPL_PINMUX_CLKREQ_OUT_OVRD_EN BIT(9) -#define APPL_PINMUX_CLKREQ_OUT_OVRD BIT(10) #define APPL_CTRL 0x4 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) @@ -1193,8 +1191,8 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, if (!pcie->supports_clkreq) { val = appl_readl(pcie, APPL_PINMUX); - val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN; - val |= APPL_PINMUX_CLKREQ_OUT_OVRD; + val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN; + val &= ~APPL_PINMUX_CLKREQ_OVERRIDE; appl_writel(pcie, val, APPL_PINMUX); }
Corrects the programming to provide REFCLK to the downstream device when there is no CLKREQ sideband signal routing present from root port to the endpont. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- drivers/pci/controller/dwc/pcie-tegra194.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)