diff mbox series

[RESEND,v2,1/4] dt-bindings: power: add Amlogic secure power domains bindings

Message ID 1570695678-42623-2-git-send-email-jianxin.pan@amlogic.com (mailing list archive)
State New, archived
Headers show
Series arm64: meson: add support for A1 Power Domains | expand

Commit Message

Jianxin Pan Oct. 10, 2019, 8:21 a.m. UTC 
Add the bindings for the Amlogic Secure power domains, controlling the
secure power domains.

The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
power domain registers are in secure world.

Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
---
 .../bindings/power/amlogic,meson-sec-pwrc.yaml     | 42 ++++++++++++++++++++++
 include/dt-bindings/power/meson-a1-power.h         | 32 +++++++++++++++++
 2 files changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
 create mode 100644 include/dt-bindings/power/meson-a1-power.h

Comments

Rob Herring Oct. 14, 2019, 5:39 p.m. UTC | #1 
On Thu, Oct 10, 2019 at 04:21:15AM -0400, Jianxin Pan wrote:
> Add the bindings for the Amlogic Secure power domains, controlling the
> secure power domains.
> 
> The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
> power domain registers are in secure world.
> 
> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> ---
>  .../bindings/power/amlogic,meson-sec-pwrc.yaml     | 42 ++++++++++++++++++++++
>  include/dt-bindings/power/meson-a1-power.h         | 32 +++++++++++++++++
>  2 files changed, 74 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
>  create mode 100644 include/dt-bindings/power/meson-a1-power.h
> 
> diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
> new file mode 100644
> index 00000000..88d8261
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
> @@ -0,0 +1,42 @@
> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +# Copyright (c) 2019 Amlogic, Inc
> +# Author: Jianxin Pan <jianxin.pan@amlogic.com>
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/power/amlogic,meson-sec-pwrc.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Amlogic Meson Secure Power Domains
> +
> +maintainers:
> +  - Jianxin Pan <jianxin.pan@amlogic.com>
> +
> +description: |+
> +  Meson Secure Power Domains used in A1/C1 SoCs.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - amlogic,meson-a1-pwrc
> +
> +  "#power-domain-cells":
> +    const: 1
> +
> +  secure-monitor:
> +    description: phandle to the secure-monitor node
> +    $ref: /schemas/types.yaml#/definitions/phandle

Why not just a child node of this node?

Rob
Jianxin Pan Oct. 16, 2019, 11:26 a.m. UTC | #2 
Hi Rob,

On 2019/10/15 1:39, Rob Herring wrote:
> On Thu, Oct 10, 2019 at 04:21:15AM -0400, Jianxin Pan wrote:
>> Add the bindings for the Amlogic Secure power domains, controlling the
>> secure power domains.
>>
>> The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
>> power domain registers are in secure world.
>>
>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>> ---
>>  .../bindings/power/amlogic,meson-sec-pwrc.yaml     | 42 ++++++++++++++++++++++
>>  include/dt-bindings/power/meson-a1-power.h         | 32 +++++++++++++++++
>>  2 files changed, 74 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
>> +
>> +  secure-monitor:
>> +    description: phandle to the secure-monitor node
>> +    $ref: /schemas/types.yaml#/definitions/phandle
> 
> Why not just a child node of this node?
> 
Thanks for the review.

I followed the style of the previous series of meson：

  46         efuse: efuse {                                                           
  47                 compatible = "amlogic,meson-gxbb-efuse";                         
  48                 clocks = <&clkc CLKID_EFUSE>;                                    
  49                 #address-cells = <1>;                                            
  50                 #size-cells = <1>;                                               
  51                 read-only;                                                       
  52                 secure-monitor = <&sm>;                                          
  53         };

> Rob
> 
> .
>
Rob Herring Oct. 25, 2019, 8:19 p.m. UTC | #3 
On Wed, Oct 16, 2019 at 6:26 AM Jianxin Pan <jianxin.pan@amlogic.com> wrote:
>
> Hi Rob,
>
> On 2019/10/15 1:39, Rob Herring wrote:
> > On Thu, Oct 10, 2019 at 04:21:15AM -0400, Jianxin Pan wrote:
> >> Add the bindings for the Amlogic Secure power domains, controlling the
> >> secure power domains.
> >>
> >> The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
> >> power domain registers are in secure world.
> >>
> >> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> >> ---
> >>  .../bindings/power/amlogic,meson-sec-pwrc.yaml     | 42 ++++++++++++++++++++++
> >>  include/dt-bindings/power/meson-a1-power.h         | 32 +++++++++++++++++
> >>  2 files changed, 74 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
> >> +
> >> +  secure-monitor:
> >> +    description: phandle to the secure-monitor node
> >> +    $ref: /schemas/types.yaml#/definitions/phandle
> >
> > Why not just a child node of this node?
> >
> Thanks for the review.
>
> I followed the style of the previous series of meson：
>
>   46         efuse: efuse {
>   47                 compatible = "amlogic,meson-gxbb-efuse";
>   48                 clocks = <&clkc CLKID_EFUSE>;
>   49                 #address-cells = <1>;
>   50                 #size-cells = <1>;
>   51                 read-only;
>   52                 secure-monitor = <&sm>;
>   53         };

Looks like that was not reviewed by me and is only in linux-next.
Please make functions exposed by secure world a child of the secure
firmware node.

Really for power domains, you only need to add a '#power-domain-cells'
property to the secure monitor node.

Rob
Jianxin Pan Oct. 28, 2019, 11:11 a.m. UTC | #4 
Hi Rob,

On 2019/10/26 4:19, Rob Herring wrote:
> On Wed, Oct 16, 2019 at 6:26 AM Jianxin Pan <jianxin.pan@amlogic.com> wrote:
>>
>> Hi Rob,
>>
>> On 2019/10/15 1:39, Rob Herring wrote:
>>> On Thu, Oct 10, 2019 at 04:21:15AM -0400, Jianxin Pan wrote:
>>>> Add the bindings for the Amlogic Secure power domains, controlling the
>>>> secure power domains.
>>>>
>>>> The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
>>>> power domain registers are in secure world.
>>>>
>>>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>>>> ---
>>>>  .../bindings/power/amlogic,meson-sec-pwrc.yaml     | 42 ++++++++++++++++++++++
>>>>  include/dt-bindings/power/meson-a1-power.h         | 32 +++++++++++++++++
>>>>  2 files changed, 74 insertions(+)
>>>>  create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
>>>> +
>>>> +  secure-monitor:
>>>> +    description: phandle to the secure-monitor node
>>>> +    $ref: /schemas/types.yaml#/definitions/phandle
>>>
>>> Why not just a child node of this node?
>>>
>> Thanks for the review.
>>
>> I followed the style of the previous series of meson：
>>
>>   46         efuse: efuse {
>>   47                 compatible = "amlogic,meson-gxbb-efuse";
>>   48                 clocks = <&clkc CLKID_EFUSE>;
>>   49                 #address-cells = <1>;
>>   50                 #size-cells = <1>;
>>   51                 read-only;
>>   52                 secure-monitor = <&sm>;
>>   53         };
> 
> Looks like that was not reviewed by me and is only in linux-next.
> Please make functions exposed by secure world a child of the secure
> firmware node.
> 
> Really for power domains, you only need to add a '#power-domain-cells'
> property to the secure monitor node.
> 
OK, I will update them in the next version. 
Thanks for the review.
> Rob
> 
> .
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
new file mode 100644
index 00000000..88d8261
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
@@ -0,0 +1,42 @@ 
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+# Copyright (c) 2019 Amlogic, Inc
+# Author: Jianxin Pan <jianxin.pan@amlogic.com>
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/amlogic,meson-sec-pwrc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson Secure Power Domains
+
+maintainers:
+  - Jianxin Pan <jianxin.pan@amlogic.com>
+
+description: |+
+  Meson Secure Power Domains used in A1/C1 SoCs.
+
+properties:
+  compatible:
+    enum:
+      - amlogic,meson-a1-pwrc
+
+  "#power-domain-cells":
+    const: 1
+
+  secure-monitor:
+    description: phandle to the secure-monitor node
+    $ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+  - compatible
+  - "#power-domain-cells"
+  - secure-monitor
+
+examples:
+  - |
+    pwrc: power-controller {
+          compatible = "amlogic,meson-a1-pwrc";
+          #power-domain-cells = <1>;
+          secure-monitor = <&sm>;
+    };
+
+
diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h
new file mode 100644
index 00000000..6cf50bf
--- /dev/null
+++ b/include/dt-bindings/power/meson-a1-power.h
@@ -0,0 +1,32 @@ 
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc.
+ * Author: Jianxin Pan <jianxin.pan@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_MESON_A1_POWER_H
+#define _DT_BINDINGS_MESON_A1_POWER_H
+
+#define PWRC_DSPA_ID	8
+#define PWRC_DSPB_ID	9
+#define PWRC_UART_ID	10
+#define PWRC_DMC_ID	11
+#define PWRC_I2C_ID	12
+#define PWRC_PSRAM_ID	13
+#define PWRC_ACODEC_ID	14
+#define PWRC_AUDIO_ID	15
+#define PWRC_OTP_ID	16
+#define PWRC_DMA_ID	17
+#define PWRC_SD_EMMC_ID	18
+#define PWRC_RAMA_ID	19
+#define PWRC_RAMB_ID	20
+#define PWRC_IR_ID	21
+#define PWRC_SPICC_ID	22
+#define PWRC_SPIFC_ID	23
+#define PWRC_USB_ID	24
+#define PWRC_NIC_ID	25
+#define PWRC_PDMIN_ID	26
+#define PWRC_RSA_ID	27
+#define PWRC_MAX_ID	28
+
+#endif