[03/12] riscv: poison SBI calls for M-mode

Message ID	20191028121043.22934-4-hch@lst.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=R/Cm=YV=lists.infradead.org=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D1F92214D9 From: Christoph Hellwig <hch@lst.de> To: Palmer Dabbelt <palmer@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com> Subject: [PATCH 03/12] riscv: poison SBI calls for M-mode Date: Mon, 28 Oct 2019 13:10:34 +0100 Message-Id: <20191028121043.22934-4-hch@lst.de> In-Reply-To: <20191028121043.22934-1-hch@lst.de> References: <20191028121043.22934-1-hch@lst.de> MIME-Version: 1.0 Precedence: list Cc: Anup Patel <anup@brainfault.org>, Damien Le Moal <damien.lemoal@wdc.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org
Series	[01/12] riscv: abstract out CSR names for supervisor vs machine mode \| expand [01/12] riscv: abstract out CSR names for supervisor vs machine mode [02/12] riscv: don't allow selecting SBI based drivers for M-mode [03/12] riscv: poison SBI calls for M-mode [04/12] riscv: cleanup the default power off implementation [05/12] riscv: implement remote sfence.i using IPIs [06/12] riscv: add support for MMIO access to the timer registers [07/12] riscv: provide native clint access for M-mode [08/12] riscv: read the hart ID from mhartid on boot [09/12] riscv: clear the instruction cache and all registers when booting [10/12] riscv: add nommu support [11/12] riscv: provide a flat image loader [12/12] riscv: disable the EFI PECOFF header for M-mode

Message ID

20191028121043.22934-4-hch@lst.de (mailing list archive)

State

New, archived

Headers

DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D1F92214D9
From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
 Paul Walmsley <paul.walmsley@sifive.com>
Subject: [PATCH 03/12] riscv: poison SBI calls for M-mode
Date: Mon, 28 Oct 2019 13:10:34 +0100
Message-Id: <20191028121043.22934-4-hch@lst.de>
In-Reply-To: <20191028121043.22934-1-hch@lst.de>
References: <20191028121043.22934-1-hch@lst.de>
MIME-Version: 1.0
Precedence: list
Cc: Anup Patel <anup@brainfault.org>, Damien Le Moal <damien.lemoal@wdc.com>,
 linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Errors-To: 
 linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org

Series

[01/12] riscv: abstract out CSR names for supervisor vs machine mode | expand

Commit Message

Christoph Hellwig Oct. 28, 2019, 12:10 p.m. UTC

There is no SBI when we run in M-mode, so fail the compile for any code
trying to use SBI calls.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/include/asm/sbi.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Comments

Paul Walmsley Oct. 31, 2019, 11:55 p.m. UTC | #1

On Mon, 28 Oct 2019, Christoph Hellwig wrote:

> There is no SBI when we run in M-mode, so fail the compile for any code
> trying to use SBI calls.
> 
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> Reviewed-by: Anup Patel <anup@brainfault.org>

Thanks, queued for v5.5-rc.


- Paul

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 21134b3ef404..b167af3e7470 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -8,6 +8,7 @@ 
 
 #include <linux/types.h>
 
+#ifdef CONFIG_RISCV_SBI
 #define SBI_SET_TIMER 0
 #define SBI_CONSOLE_PUTCHAR 1
 #define SBI_CONSOLE_GETCHAR 2
@@ -93,5 +94,5 @@  static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
 {
 	SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
 }
-
-#endif
+#endif /* CONFIG_RISCV_SBI */
+#endif /* _ASM_RISCV_SBI_H */

[03/12] riscv: poison SBI calls for M-mode

Commit Message

Comments

Patch