| Message ID | 20191106141424.27244-2-edgar.iglesias@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/microblaze: Plug tcg temp leaks | expand |
On 11/6/19 3:14 PM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Plug TCG temp leaks for loads/stores. > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > target/microblaze/translate.c | 30 ++++++++++++++++++++++++------ > 1 file changed, 24 insertions(+), 6 deletions(-) > > diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c > index 761f535357..ba143ede5f 100644 > --- a/target/microblaze/translate.c > +++ b/target/microblaze/translate.c > @@ -967,12 +967,14 @@ static void dec_load(DisasContext *dc) > 10 -> 10 > 11 -> 00 */ > TCGv low = tcg_temp_new(); > + TCGv t3 = tcg_const_tl(3); > > tcg_gen_andi_tl(low, addr, 3); > - tcg_gen_sub_tl(low, tcg_const_tl(3), low); > + tcg_gen_sub_tl(low, t3, low); > tcg_gen_andi_tl(addr, addr, ~3); > tcg_gen_or_tl(addr, addr, low); > tcg_temp_free(low); > + tcg_temp_free(t3); > break; > } > > @@ -1006,9 +1008,16 @@ static void dec_load(DisasContext *dc) > tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); > > if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { > + TCGv_i32 t0 = tcg_const_i32(0); > + TCGv_i32 treg = tcg_const_i32(dc->rd); > + TCGv_i32 tsize = tcg_const_i32(size - 1); > + > tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); > - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), > - tcg_const_i32(0), tcg_const_i32(size - 1)); > + gen_helper_memalign(cpu_env, addr, treg, t0, tsize); > + > + tcg_temp_free_i32(t0); > + tcg_temp_free_i32(treg); > + tcg_temp_free_i32(tsize); > } > > if (ex) { > @@ -1100,12 +1109,14 @@ static void dec_store(DisasContext *dc) > 10 -> 10 > 11 -> 00 */ > TCGv low = tcg_temp_new(); > + TCGv t3 = tcg_const_tl(3); > > tcg_gen_andi_tl(low, addr, 3); > - tcg_gen_sub_tl(low, tcg_const_tl(3), low); > + tcg_gen_sub_tl(low, t3, low); > tcg_gen_andi_tl(addr, addr, ~3); > tcg_gen_or_tl(addr, addr, low); > tcg_temp_free(low); > + tcg_temp_free(t3); > break; > } > > @@ -1124,6 +1135,10 @@ static void dec_store(DisasContext *dc) > > /* Verify alignment if needed. */ > if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { > + TCGv_i32 t1 = tcg_const_i32(1); > + TCGv_i32 treg = tcg_const_i32(dc->rd); > + TCGv_i32 tsize = tcg_const_i32(size - 1); > + > tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); > /* FIXME: if the alignment is wrong, we should restore the value > * in memory. One possible way to achieve this is to probe > @@ -1131,8 +1146,11 @@ static void dec_store(DisasContext *dc) > * the alignment checks in between the probe and the mem > * access. > */ > - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), > - tcg_const_i32(1), tcg_const_i32(size - 1)); > + gen_helper_memalign(cpu_env, addr, treg, t1, tsize); > + > + tcg_temp_free_i32(t1); > + tcg_temp_free_i32(treg); > + tcg_temp_free_i32(tsize); > } > > if (ex) { > Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
On 11/6/19 3:14 PM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Plug TCG temp leaks for loads/stores. > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > target/microblaze/translate.c | 30 ++++++++++++++++++++++++------ > 1 file changed, 24 insertions(+), 6 deletions(-) > > diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c > index 761f535357..ba143ede5f 100644 > --- a/target/microblaze/translate.c > +++ b/target/microblaze/translate.c > @@ -967,12 +967,14 @@ static void dec_load(DisasContext *dc) > 10 -> 10 > 11 -> 00 */ > TCGv low = tcg_temp_new(); > + TCGv t3 = tcg_const_tl(3); > > tcg_gen_andi_tl(low, addr, 3); > - tcg_gen_sub_tl(low, tcg_const_tl(3), low); > + tcg_gen_sub_tl(low, t3, low); For this one, I think you can use tcg_gen_subfi_tl(low, 3, low) > tcg_gen_andi_tl(addr, addr, ~3); > tcg_gen_or_tl(addr, addr, low); > tcg_temp_free(low); > + tcg_temp_free(t3); > break; > } > > @@ -1006,9 +1008,16 @@ static void dec_load(DisasContext *dc) > tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); > > if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { > + TCGv_i32 t0 = tcg_const_i32(0); > + TCGv_i32 treg = tcg_const_i32(dc->rd); > + TCGv_i32 tsize = tcg_const_i32(size - 1); > + > tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); > - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), > - tcg_const_i32(0), tcg_const_i32(size - 1)); > + gen_helper_memalign(cpu_env, addr, treg, t0, tsize); > + > + tcg_temp_free_i32(t0); > + tcg_temp_free_i32(treg); > + tcg_temp_free_i32(tsize); > } > > if (ex) { > @@ -1100,12 +1109,14 @@ static void dec_store(DisasContext *dc) > 10 -> 10 > 11 -> 00 */ > TCGv low = tcg_temp_new(); > + TCGv t3 = tcg_const_tl(3); > > tcg_gen_andi_tl(low, addr, 3); > - tcg_gen_sub_tl(low, tcg_const_tl(3), low); > + tcg_gen_sub_tl(low, t3, low); Same here. With or without those modifications: Reviewed-by: Luc Michel <luc.michel@greensocs.com> > tcg_gen_andi_tl(addr, addr, ~3); > tcg_gen_or_tl(addr, addr, low); > tcg_temp_free(low); > + tcg_temp_free(t3); > break; > } > > @@ -1124,6 +1135,10 @@ static void dec_store(DisasContext *dc) > > /* Verify alignment if needed. */ > if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { > + TCGv_i32 t1 = tcg_const_i32(1); > + TCGv_i32 treg = tcg_const_i32(dc->rd); > + TCGv_i32 tsize = tcg_const_i32(size - 1); > + > tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); > /* FIXME: if the alignment is wrong, we should restore the value > * in memory. One possible way to achieve this is to probe > @@ -1131,8 +1146,11 @@ static void dec_store(DisasContext *dc) > * the alignment checks in between the probe and the mem > * access. > */ > - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), > - tcg_const_i32(1), tcg_const_i32(size - 1)); > + gen_helper_memalign(cpu_env, addr, treg, t1, tsize); > + > + tcg_temp_free_i32(t1); > + tcg_temp_free_i32(treg); > + tcg_temp_free_i32(tsize); > } > > if (ex) { >
On Wed, Nov 6, 2019 at 6:14 AM Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote: > > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Plug TCG temp leaks for loads/stores. > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/microblaze/translate.c | 30 ++++++++++++++++++++++++------ > 1 file changed, 24 insertions(+), 6 deletions(-) > > diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c > index 761f535357..ba143ede5f 100644 > --- a/target/microblaze/translate.c > +++ b/target/microblaze/translate.c > @@ -967,12 +967,14 @@ static void dec_load(DisasContext *dc) > 10 -> 10 > 11 -> 00 */ > TCGv low = tcg_temp_new(); > + TCGv t3 = tcg_const_tl(3); > > tcg_gen_andi_tl(low, addr, 3); > - tcg_gen_sub_tl(low, tcg_const_tl(3), low); > + tcg_gen_sub_tl(low, t3, low); > tcg_gen_andi_tl(addr, addr, ~3); > tcg_gen_or_tl(addr, addr, low); > tcg_temp_free(low); > + tcg_temp_free(t3); > break; > } > > @@ -1006,9 +1008,16 @@ static void dec_load(DisasContext *dc) > tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); > > if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { > + TCGv_i32 t0 = tcg_const_i32(0); > + TCGv_i32 treg = tcg_const_i32(dc->rd); > + TCGv_i32 tsize = tcg_const_i32(size - 1); > + > tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); > - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), > - tcg_const_i32(0), tcg_const_i32(size - 1)); > + gen_helper_memalign(cpu_env, addr, treg, t0, tsize); > + > + tcg_temp_free_i32(t0); > + tcg_temp_free_i32(treg); > + tcg_temp_free_i32(tsize); > } > > if (ex) { > @@ -1100,12 +1109,14 @@ static void dec_store(DisasContext *dc) > 10 -> 10 > 11 -> 00 */ > TCGv low = tcg_temp_new(); > + TCGv t3 = tcg_const_tl(3); > > tcg_gen_andi_tl(low, addr, 3); > - tcg_gen_sub_tl(low, tcg_const_tl(3), low); > + tcg_gen_sub_tl(low, t3, low); > tcg_gen_andi_tl(addr, addr, ~3); > tcg_gen_or_tl(addr, addr, low); > tcg_temp_free(low); > + tcg_temp_free(t3); > break; > } > > @@ -1124,6 +1135,10 @@ static void dec_store(DisasContext *dc) > > /* Verify alignment if needed. */ > if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { > + TCGv_i32 t1 = tcg_const_i32(1); > + TCGv_i32 treg = tcg_const_i32(dc->rd); > + TCGv_i32 tsize = tcg_const_i32(size - 1); > + > tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); > /* FIXME: if the alignment is wrong, we should restore the value > * in memory. One possible way to achieve this is to probe > @@ -1131,8 +1146,11 @@ static void dec_store(DisasContext *dc) > * the alignment checks in between the probe and the mem > * access. > */ > - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), > - tcg_const_i32(1), tcg_const_i32(size - 1)); > + gen_helper_memalign(cpu_env, addr, treg, t1, tsize); > + > + tcg_temp_free_i32(t1); > + tcg_temp_free_i32(treg); > + tcg_temp_free_i32(tsize); > } > > if (ex) { > -- > 2.20.1 > >
On 11/6/19 3:14 PM, Edgar E. Iglesias wrote: > @@ -967,12 +967,14 @@ static void dec_load(DisasContext *dc) > 10 -> 10 > 11 -> 00 */ > TCGv low = tcg_temp_new(); > + TCGv t3 = tcg_const_tl(3); > > tcg_gen_andi_tl(low, addr, 3); > - tcg_gen_sub_tl(low, tcg_const_tl(3), low); > + tcg_gen_sub_tl(low, t3, low); > tcg_gen_andi_tl(addr, addr, ~3); > tcg_gen_or_tl(addr, addr, low); > tcg_temp_free(low); > + tcg_temp_free(t3); > break; While Luc correctly notes that tcg_gen_subfi_tl() may be used here, I will note (1) there's a typo in the comment (not 2->2, but 2->1), and (2) that this whole section can be done with tcg_gen_xori_tl(addr, addr, 3); Similarly in dec_store. The other changes in this patch around gen_helper_memalign are ok. r~
On Thu, Nov 07, 2019 at 03:19:20PM +0100, Richard Henderson wrote: > On 11/6/19 3:14 PM, Edgar E. Iglesias wrote: > > @@ -967,12 +967,14 @@ static void dec_load(DisasContext *dc) > > 10 -> 10 > > 11 -> 00 */ > > TCGv low = tcg_temp_new(); > > + TCGv t3 = tcg_const_tl(3); > > > > tcg_gen_andi_tl(low, addr, 3); > > - tcg_gen_sub_tl(low, tcg_const_tl(3), low); > > + tcg_gen_sub_tl(low, t3, low); > > tcg_gen_andi_tl(addr, addr, ~3); > > tcg_gen_or_tl(addr, addr, low); > > tcg_temp_free(low); > > + tcg_temp_free(t3); > > break; > > While Luc correctly notes that tcg_gen_subfi_tl() may be used here, I will note > (1) there's a typo in the comment (not 2->2, but 2->1), and (2) that this whole > section can be done with > > tcg_gen_xori_tl(addr, addr, 3); Nice! I'll send out a new version shortly. Best regards, Edgar > > Similarly in dec_store. > > The other changes in this patch around gen_helper_memalign are ok. > > > r~
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 761f535357..ba143ede5f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -967,12 +967,14 @@ static void dec_load(DisasContext *dc) 10 -> 10 11 -> 00 */ TCGv low = tcg_temp_new(); + TCGv t3 = tcg_const_tl(3); tcg_gen_andi_tl(low, addr, 3); - tcg_gen_sub_tl(low, tcg_const_tl(3), low); + tcg_gen_sub_tl(low, t3, low); tcg_gen_andi_tl(addr, addr, ~3); tcg_gen_or_tl(addr, addr, low); tcg_temp_free(low); + tcg_temp_free(t3); break; } @@ -1006,9 +1008,16 @@ static void dec_load(DisasContext *dc) tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { + TCGv_i32 t0 = tcg_const_i32(0); + TCGv_i32 treg = tcg_const_i32(dc->rd); + TCGv_i32 tsize = tcg_const_i32(size - 1); + tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), - tcg_const_i32(0), tcg_const_i32(size - 1)); + gen_helper_memalign(cpu_env, addr, treg, t0, tsize); + + tcg_temp_free_i32(t0); + tcg_temp_free_i32(treg); + tcg_temp_free_i32(tsize); } if (ex) { @@ -1100,12 +1109,14 @@ static void dec_store(DisasContext *dc) 10 -> 10 11 -> 00 */ TCGv low = tcg_temp_new(); + TCGv t3 = tcg_const_tl(3); tcg_gen_andi_tl(low, addr, 3); - tcg_gen_sub_tl(low, tcg_const_tl(3), low); + tcg_gen_sub_tl(low, t3, low); tcg_gen_andi_tl(addr, addr, ~3); tcg_gen_or_tl(addr, addr, low); tcg_temp_free(low); + tcg_temp_free(t3); break; } @@ -1124,6 +1135,10 @@ static void dec_store(DisasContext *dc) /* Verify alignment if needed. */ if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { + TCGv_i32 t1 = tcg_const_i32(1); + TCGv_i32 treg = tcg_const_i32(dc->rd); + TCGv_i32 tsize = tcg_const_i32(size - 1); + tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); /* FIXME: if the alignment is wrong, we should restore the value * in memory. One possible way to achieve this is to probe @@ -1131,8 +1146,11 @@ static void dec_store(DisasContext *dc) * the alignment checks in between the probe and the mem * access. */ - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), - tcg_const_i32(1), tcg_const_i32(size - 1)); + gen_helper_memalign(cpu_env, addr, treg, t1, tsize); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(treg); + tcg_temp_free_i32(tsize); } if (ex) {