| Message ID | 20191203034519.5640-6-chris.brandt@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | spi: Add Renesas SPIBSC controller | expand |
Hi Chris, On Tue, Dec 3, 2019 at 4:46 AM Chris Brandt <chris.brandt@renesas.com> wrote: > Add SPIBSC Device support for RZ/A2. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Thanks for your patch! > --- a/arch/arm/boot/dts/r7s9210.dtsi > +++ b/arch/arm/boot/dts/r7s9210.dtsi > @@ -68,6 +68,16 @@ > cache-level = <2>; > }; > > + spibsc: spi@1f800000 { > + compatible = "renesas,r7s9210-spibsc", "renesas,spibsc"; > + reg = <0x1f800000 0x8c>, <0x20000000 0x10000000 >; Any specific reason you're using 0x8c, not 0x100? > + clocks = <&cpg CPG_MOD 83>; > + power-domains = <&cpg>; > + #address-cells = <1>; > + #size-cells = <0>; interrupts? > + status = "disabled"; > + }; > + > scif0: serial@e8007000 { > compatible = "renesas,scif-r7s9210"; > reg = <0xe8007000 0x18>; Gr{oetje,eeting}s, Geert
Hi Geert, On Tue, Dec 3, 2019, Geert Uytterhoeven wrote: > > + reg = <0x1f800000 0x8c>, <0x20000000 > > + 0x10000000 >; > > Any specific reason you're using 0x8c, not 0x100? Because....I keep forgetting what is the latest 'correct' size: A. The exact size of the register range or B. The size rounded up to look nicer > > + clocks = <&cpg CPG_MOD 83>; > > + power-domains = <&cpg>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > interrupts? I guess I can put it in there just to correctly 'document the hardware' in the Device Tree file. Chris
Hi Chris, On Tue, Dec 3, 2019 at 11:38 PM Chris Brandt <Chris.Brandt@renesas.com> wrote: > On Tue, Dec 3, 2019, Geert Uytterhoeven wrote: > > > + reg = <0x1f800000 0x8c>, <0x20000000 > > > + 0x10000000 >; > > > > Any specific reason you're using 0x8c, not 0x100? > > Because....I keep forgetting what is the latest 'correct' size: > A. The exact size of the register range > or > B. The size rounded up to look nicer C. The size used by the on-chip address decoder providing the module's select signal? I doubt that's not a power of two ;-) Gr{oetje,eeting}s, Geert
Hi Geert, On Wed, Dec 4, 2019, Geert Uytterhoeven wrote: > > Because....I keep forgetting what is the latest 'correct' size: > > A. The exact size of the register range or > > B. The size rounded up to look nicer > > C. The size used by the on-chip address decoder providing the module's > select signal? I doubt that's not a power of two ;-) Point taken :) I'll change it. Chris
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi index 72b79770e336..ac4949c9e47a 100644 --- a/arch/arm/boot/dts/r7s9210.dtsi +++ b/arch/arm/boot/dts/r7s9210.dtsi @@ -68,6 +68,16 @@ cache-level = <2>; }; + spibsc: spi@1f800000 { + compatible = "renesas,r7s9210-spibsc", "renesas,spibsc"; + reg = <0x1f800000 0x8c>, <0x20000000 0x10000000 >; + clocks = <&cpg CPG_MOD 83>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif0: serial@e8007000 { compatible = "renesas,scif-r7s9210"; reg = <0xe8007000 0x18>;
Add SPIBSC Device support for RZ/A2. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> --- arch/arm/boot/dts/r7s9210.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)