| Message ID | 20191202111253.94872-1-jian.hu@amlogic.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: meson-a1: add I2C nodes | expand |
Hi Jian, Jian Hu <jian.hu@amlogic.com> writes: > There are four I2C controllers in A1 series, > Share the same comptible with AXG.The I2C nodes > depend on pinmux and clock controller. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > --- > arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 149 ++++++++++++++++++++++ > 1 file changed, 149 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > index eab2ecd36aa8..d0a73d953f5e 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > @@ -16,6 +16,13 @@ > #address-cells = <2>; > #size-cells = <2>; > > + aliases { > + i2c0 = &i2c0; > + i2c1 = &i2c1; > + i2c2 = &i2c2; > + i2c3 = &i2c3; > + }; > + > cpus { > #address-cells = <2>; > #size-cells = <0>; > @@ -117,6 +124,46 @@ > }; > }; > > + i2c0: i2c@1400 { > + compatible = "amlogic,meson-axg-i2c"; > + reg = <0x0 0x1400 0x0 0x24>; The AXG DT files use 0x20 for the length. You are using 0x24. I don't see any additional registers added to the driver, so this doesn't look right. > + interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&clkc_periphs CLKID_I2C_M_A>; > + status = "disabled"; > + }; > + > + i2c1: i2c@5c00 { > + compatible = "amlogic,meson-axg-i2c"; > + reg = <0x0 0x5c00 0x0 0x24>; > + interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&clkc_periphs CLKID_I2C_M_B>; > + status = "disabled"; > + }; > + > + i2c2: i2c@6800 { > + compatible = "amlogic,meson-axg-i2c"; > + reg = <0x0 0x6800 0x0 0x24>; > + interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&clkc_periphs CLKID_I2C_M_C>; > + status = "disabled"; > + }; > + > + i2c3: i2c@6c00 { > + compatible = "amlogic,meson-axg-i2c"; > + reg = <0x0 0x6c00 0x0 0x24>; > + interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&clkc_periphs CLKID_I2C_M_D>; > + status = "disabled"; > + }; > + > uart_AO: serial@1c00 { > compatible = "amlogic,meson-gx-uart", > "amlogic,meson-ao-uart"; > @@ -171,3 +218,105 @@ > #clock-cells = <0>; > }; > }; > + > +&periphs_pinctrl { > + i2c0_f11_pins:i2c0-f11 { > + mux { > + groups = "i2c0_sck_f11", > + "i2c0_sda_f12"; > + function = "i2c0"; > + bias-pull-up; > + drive-strength-microamp = <3000>; Can you also add some comment to the changelog about the need for drive-strength compared to AXG. > + }; > + }; Kevin
Hi Kevin Thanks for your review On 2019/12/10 6:54, Kevin Hilman wrote: > Hi Jian, > > Jian Hu <jian.hu@amlogic.com> writes: > >> There are four I2C controllers in A1 series, >> Share the same comptible with AXG.The I2C nodes >> depend on pinmux and clock controller. >> >> Signed-off-by: Jian Hu <jian.hu@amlogic.com> >> --- >> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 149 ++++++++++++++++++++++ >> 1 file changed, 149 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> index eab2ecd36aa8..d0a73d953f5e 100644 >> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> @@ -16,6 +16,13 @@ >> #address-cells = <2>; >> #size-cells = <2>; >> >> + aliases { >> + i2c0 = &i2c0; >> + i2c1 = &i2c1; >> + i2c2 = &i2c2; >> + i2c3 = &i2c3; >> + }; >> + >> cpus { >> #address-cells = <2>; >> #size-cells = <0>; >> @@ -117,6 +124,46 @@ >> }; >> }; >> >> + i2c0: i2c@1400 { >> + compatible = "amlogic,meson-axg-i2c"; >> + reg = <0x0 0x1400 0x0 0x24>; > > The AXG DT files use 0x20 for the length. You are using 0x24. I don't > see any additional registers added to the driver, so this doesn't look right. In fact, For G12 series and A1, the length should be 0x24. A new register is added, And it is for IRQ handler timeout. If the transmission is exceeding a limited time, it will abort the transmission.Now the function is not used, There is completion to deal the timeout in the driver. I will set the length 0x20 becouse of the new register is not used. > >> + interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&clkc_periphs CLKID_I2C_M_A>; >> + status = "disabled"; >> + }; >> + >> + i2c1: i2c@5c00 { >> + compatible = "amlogic,meson-axg-i2c"; >> + reg = <0x0 0x5c00 0x0 0x24>; >> + interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&clkc_periphs CLKID_I2C_M_B>; >> + status = "disabled"; >> + }; >> + >> + i2c2: i2c@6800 { >> + compatible = "amlogic,meson-axg-i2c"; >> + reg = <0x0 0x6800 0x0 0x24>; >> + interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&clkc_periphs CLKID_I2C_M_C>; >> + status = "disabled"; >> + }; >> + >> + i2c3: i2c@6c00 { >> + compatible = "amlogic,meson-axg-i2c"; >> + reg = <0x0 0x6c00 0x0 0x24>; >> + interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&clkc_periphs CLKID_I2C_M_D>; >> + status = "disabled"; >> + }; >> + >> uart_AO: serial@1c00 { >> compatible = "amlogic,meson-gx-uart", >> "amlogic,meson-ao-uart"; >> @@ -171,3 +218,105 @@ >> #clock-cells = <0>; >> }; >> }; >> + >> +&periphs_pinctrl { >> + i2c0_f11_pins:i2c0-f11 { >> + mux { >> + groups = "i2c0_sck_f11", >> + "i2c0_sda_f12"; >> + function = "i2c0"; >> + bias-pull-up; >> + drive-strength-microamp = <3000>; > > Can you also add some comment to the changelog about the need for > drive-strength compared to AXG. OK, Drive strength function is added for GPIO pins from G12 series. So does A1 series. > >> + }; >> + }; > > Kevin > > . >
On Mon 02 Dec 2019 at 12:12, Jian Hu <jian.hu@amlogic.com> wrote: > There are four I2C controllers in A1 series, > Share the same comptible with AXG.The I2C nodes > depend on pinmux and clock controller. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > --- > arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 149 ++++++++++++++++++++++ > 1 file changed, 149 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > index eab2ecd36aa8..d0a73d953f5e 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > @@ -16,6 +16,13 @@ > #address-cells = <2>; > #size-cells = <2>; > > + aliases { > + i2c0 = &i2c0; > + i2c1 = &i2c1; > + i2c2 = &i2c2; > + i2c3 = &i2c3; > + }; > + I wonder if assigning i2c bus alias in the SoC dtsi is such a good idea. Such aliases are usually assigned as needed by each board design: meson-a1-ad401.dts in your case.
Jian Hu <jian.hu@amlogic.com> writes: > Hi Kevin > > Thanks for your review > > On 2019/12/10 6:54, Kevin Hilman wrote: >> Hi Jian, >> >> Jian Hu <jian.hu@amlogic.com> writes: >> >>> There are four I2C controllers in A1 series, >>> Share the same comptible with AXG.The I2C nodes >>> depend on pinmux and clock controller. >>> >>> Signed-off-by: Jian Hu <jian.hu@amlogic.com> >>> --- >>> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 149 ++++++++++++++++++++++ >>> 1 file changed, 149 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >>> index eab2ecd36aa8..d0a73d953f5e 100644 >>> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >>> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >>> @@ -16,6 +16,13 @@ >>> #address-cells = <2>; >>> #size-cells = <2>; >>> >>> + aliases { >>> + i2c0 = &i2c0; >>> + i2c1 = &i2c1; >>> + i2c2 = &i2c2; >>> + i2c3 = &i2c3; >>> + }; >>> + >>> cpus { >>> #address-cells = <2>; >>> #size-cells = <0>; >>> @@ -117,6 +124,46 @@ >>> }; >>> }; >>> >>> + i2c0: i2c@1400 { >>> + compatible = "amlogic,meson-axg-i2c"; >>> + reg = <0x0 0x1400 0x0 0x24>; >> >> The AXG DT files use 0x20 for the length. You are using 0x24. I don't >> see any additional registers added to the driver, so this doesn't look right. > In fact, For G12 series and A1, the length should be 0x24. A new > register is added, And it is for IRQ handler timeout. If the > transmission is exceeding a limited time, it will abort the > transmission.Now the function is not used, There is completion to deal > the timeout in the driver. I will set the length 0x20 becouse of the new > register is not used. Yes, we can extend it to 0x24 when support for the new register is added, because that will mean adding a new compatible string also. >> >>> + interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + clocks = <&clkc_periphs CLKID_I2C_M_A>; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c1: i2c@5c00 { >>> + compatible = "amlogic,meson-axg-i2c"; >>> + reg = <0x0 0x5c00 0x0 0x24>; >>> + interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + clocks = <&clkc_periphs CLKID_I2C_M_B>; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c2: i2c@6800 { >>> + compatible = "amlogic,meson-axg-i2c"; >>> + reg = <0x0 0x6800 0x0 0x24>; >>> + interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + clocks = <&clkc_periphs CLKID_I2C_M_C>; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c3: i2c@6c00 { >>> + compatible = "amlogic,meson-axg-i2c"; >>> + reg = <0x0 0x6c00 0x0 0x24>; >>> + interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + clocks = <&clkc_periphs CLKID_I2C_M_D>; >>> + status = "disabled"; >>> + }; >>> + >>> uart_AO: serial@1c00 { >>> compatible = "amlogic,meson-gx-uart", >>> "amlogic,meson-ao-uart"; >>> @@ -171,3 +218,105 @@ >>> #clock-cells = <0>; >>> }; >>> }; >>> + >>> +&periphs_pinctrl { >>> + i2c0_f11_pins:i2c0-f11 { >>> + mux { >>> + groups = "i2c0_sck_f11", >>> + "i2c0_sda_f12"; >>> + function = "i2c0"; >>> + bias-pull-up; >>> + drive-strength-microamp = <3000>; >> >> Can you also add some comment to the changelog about the need for >> drive-strength compared to AXG. > > OK, Drive strength function is added for GPIO pins from G12 series. > So does A1 series. Yes, that's what I assumed. Please add that to the changelog as one of the new features in A1 compared to AXG. Thanks, Kevin
Jerome Brunet <jbrunet@baylibre.com> writes: > On Mon 02 Dec 2019 at 12:12, Jian Hu <jian.hu@amlogic.com> wrote: > >> There are four I2C controllers in A1 series, >> Share the same comptible with AXG.The I2C nodes >> depend on pinmux and clock controller. >> >> Signed-off-by: Jian Hu <jian.hu@amlogic.com> >> --- >> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 149 ++++++++++++++++++++++ >> 1 file changed, 149 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> index eab2ecd36aa8..d0a73d953f5e 100644 >> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> @@ -16,6 +16,13 @@ >> #address-cells = <2>; >> #size-cells = <2>; >> >> + aliases { >> + i2c0 = &i2c0; >> + i2c1 = &i2c1; >> + i2c2 = &i2c2; >> + i2c3 = &i2c3; >> + }; >> + > > I wonder if assigning i2c bus alias in the SoC dtsi is such a good idea. > > Such aliases are usually assigned as needed by each board design: > meson-a1-ad401.dts in your case. Agreed. I don't think SoC-wide aliases are a great idea. Kevin
Hi jerome Thanks for your review On 2019/12/10 18:17, Jerome Brunet wrote: > > On Mon 02 Dec 2019 at 12:12, Jian Hu <jian.hu@amlogic.com> wrote: > >> There are four I2C controllers in A1 series, >> Share the same comptible with AXG.The I2C nodes >> depend on pinmux and clock controller. >> >> Signed-off-by: Jian Hu <jian.hu@amlogic.com> >> --- >> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 149 ++++++++++++++++++++++ >> 1 file changed, 149 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> index eab2ecd36aa8..d0a73d953f5e 100644 >> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> @@ -16,6 +16,13 @@ >> #address-cells = <2>; >> #size-cells = <2>; >> >> + aliases { >> + i2c0 = &i2c0; >> + i2c1 = &i2c1; >> + i2c2 = &i2c2; >> + i2c3 = &i2c3; >> + }; >> + > > I wonder if assigning i2c bus alias in the SoC dtsi is such a good idea. > > Such aliases are usually assigned as needed by each board design: > meson-a1-ad401.dts in your case. > You are right, I will set i2c bus alias in dts file. > . >
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index eab2ecd36aa8..d0a73d953f5e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -16,6 +16,13 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -117,6 +124,46 @@ }; }; + i2c0: i2c@1400 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x1400 0x0 0x24>; + interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc_periphs CLKID_I2C_M_A>; + status = "disabled"; + }; + + i2c1: i2c@5c00 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x5c00 0x0 0x24>; + interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc_periphs CLKID_I2C_M_B>; + status = "disabled"; + }; + + i2c2: i2c@6800 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x6800 0x0 0x24>; + interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc_periphs CLKID_I2C_M_C>; + status = "disabled"; + }; + + i2c3: i2c@6c00 { + compatible = "amlogic,meson-axg-i2c"; + reg = <0x0 0x6c00 0x0 0x24>; + interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc_periphs CLKID_I2C_M_D>; + status = "disabled"; + }; + uart_AO: serial@1c00 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; @@ -171,3 +218,105 @@ #clock-cells = <0>; }; }; + +&periphs_pinctrl { + i2c0_f11_pins:i2c0-f11 { + mux { + groups = "i2c0_sck_f11", + "i2c0_sda_f12"; + function = "i2c0"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c0_f9_pins:i2c0-f9 { + mux { + groups = "i2c0_sck_f9", + "i2c0_sda_f10"; + function = "i2c0"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_x_pins:i2c1-x { + mux { + groups = "i2c1_sck_x", + "i2c1_sda_x"; + function = "i2c1"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_a_pins:i2c1-a { + mux { + groups = "i2c1_sck_a", + "i2c1_sda_a"; + function = "i2c1"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_x0_pins:i2c2-x0 { + mux { + groups = "i2c2_sck_x0", + "i2c2_sda_x1"; + function = "i2c2"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_x15_pins:i2c2-x15 { + mux { + groups = "i2c2_sck_x15", + "i2c2_sda_x16"; + function = "i2c2"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_a4_pins:i2c2-a4 { + mux { + groups = "i2c2_sck_a4", + "i2c2_sda_a5"; + function = "i2c2"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_a8_pins:i2c2-a8 { + mux { + groups = "i2c2_sck_a8", + "i2c2_sda_a9"; + function = "i2c2"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_x_pins:i2c3-x { + mux { + groups = "i2c3_sck_x", + "i2c3_sda_x"; + function = "i2c3"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_f_pins:i2c3-f { + mux { + groups = "i2c3_sck_f", + "i2c3_sda_f"; + function = "i2c3"; + bias-pull-up; + drive-strength-microamp = <3000>; + }; + }; +};
There are four I2C controllers in A1 series, Share the same comptible with AXG.The I2C nodes depend on pinmux and clock controller. Signed-off-by: Jian Hu <jian.hu@amlogic.com> --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 149 ++++++++++++++++++++++ 1 file changed, 149 insertions(+)