diff mbox series

[V2] arm: dts: imx7ulp: fix reg of cpu node

Message ID 1576671574-14319-1-git-send-email-peng.fan@nxp.com (mailing list archive)
State Mainlined
Commit b8ab62ff7199fac8ce27fa4a149929034fabe7f8
Headers show
Series [V2] arm: dts: imx7ulp: fix reg of cpu node | expand

Commit Message

Peng Fan Dec. 18, 2019, 12:22 p.m. UTC
From: Peng Fan <peng.fan@nxp.com>

According to arm cpus binding doc,
"
      On 32-bit ARM v7 or later systems this property is
        required and matches the CPU MPIDR[23:0] register
        bits.

        Bits [23:0] in the reg cell must be set to
        bits [23:0] in MPIDR.

        All other bits in the reg cell must be set to 0.
"

In i.MX7ULP, the MPIDR[23:0] is 0xf00, not 0, so fix it.
Otherwise there will be warning:
"DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map"

Fixes: 20434dc92c05 ("ARM: dts: imx: add common imx7ulp dtsi support")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---

V2:
 Fix suffix, from 0 -> f00

 arch/arm/boot/dts/imx7ulp.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Fabio Estevam Dec. 18, 2019, 12:44 p.m. UTC | #1
On Wed, Dec 18, 2019 at 9:22 AM Peng Fan <peng.fan@nxp.com> wrote:
>
> From: Peng Fan <peng.fan@nxp.com>
>
> According to arm cpus binding doc,
> "
>       On 32-bit ARM v7 or later systems this property is
>         required and matches the CPU MPIDR[23:0] register
>         bits.
>
>         Bits [23:0] in the reg cell must be set to
>         bits [23:0] in MPIDR.
>
>         All other bits in the reg cell must be set to 0.
> "
>
> In i.MX7ULP, the MPIDR[23:0] is 0xf00, not 0, so fix it.
> Otherwise there will be warning:
> "DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map"
>
> Fixes: 20434dc92c05 ("ARM: dts: imx: add common imx7ulp dtsi support")
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Shawn Guo Dec. 23, 2019, 7:43 a.m. UTC | #2
On Wed, Dec 18, 2019 at 12:22:32PM +0000, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> According to arm cpus binding doc,
> "
>       On 32-bit ARM v7 or later systems this property is
>         required and matches the CPU MPIDR[23:0] register
>         bits.
> 
>         Bits [23:0] in the reg cell must be set to
>         bits [23:0] in MPIDR.
> 
>         All other bits in the reg cell must be set to 0.
> "
> 
> In i.MX7ULP, the MPIDR[23:0] is 0xf00, not 0, so fix it.
> Otherwise there will be warning:
> "DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map"
> 
> Fixes: 20434dc92c05 ("ARM: dts: imx: add common imx7ulp dtsi support")
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

For arm32 DTS patches, we use 'ARM: ...' prefix.  Fixed it up and
applied.

Shawn
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index d37a1927c88e..ab91c98f2124 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -37,10 +37,10 @@ 
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu0: cpu@0 {
+		cpu0: cpu@f00 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
-			reg = <0>;
+			reg = <0xf00>;
 		};
 	};