| Message ID | 20191219064459.20790-1-greentime.hu@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: fix scratch register clearing in M-mode. | expand |
On Thu, Dec 19, 2019 at 12:15 PM Greentime Hu <greentime.hu@sifive.com> wrote: > > This patch fixes that the sscratch register clearing in M-mode. It cleared > sscratch register in M-mode, but it should clear mscratch register. That will > cause kernel trap if the CPU core doesn't support S-mode when trying to access > sscratch. > > Fixes: 9e80635619b5 ("riscv: clear the instruction cache and all registers when booting") > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> In any case, we should always prefer accessing CSRs using CSR_xyz defines. Looks good to me. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup > --- > arch/riscv/kernel/head.S | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S > index 84a6f0a4b120..797802c73dee 100644 > --- a/arch/riscv/kernel/head.S > +++ b/arch/riscv/kernel/head.S > @@ -246,7 +246,7 @@ ENTRY(reset_regs) > li t4, 0 > li t5, 0 > li t6, 0 > - csrw sscratch, 0 > + csrw CSR_SCRATCH, 0 > > #ifdef CONFIG_FPU > csrr t0, CSR_MISA > -- > 2.17.1 > >
On Thu, 19 Dec 2019, Greentime Hu wrote: > This patch fixes that the sscratch register clearing in M-mode. It cleared > sscratch register in M-mode, but it should clear mscratch register. That will > cause kernel trap if the CPU core doesn't support S-mode when trying to access > sscratch. > > Fixes: 9e80635619b5 ("riscv: clear the instruction cache and all registers when booting") > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Thanks Greentime, queued for v5.5-rc. - Paul
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 84a6f0a4b120..797802c73dee 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -246,7 +246,7 @@ ENTRY(reset_regs) li t4, 0 li t5, 0 li t6, 0 - csrw sscratch, 0 + csrw CSR_SCRATCH, 0 #ifdef CONFIG_FPU csrr t0, CSR_MISA
This patch fixes that the sscratch register clearing in M-mode. It cleared sscratch register in M-mode, but it should clear mscratch register. That will cause kernel trap if the CPU core doesn't support S-mode when trying to access sscratch. Fixes: 9e80635619b5 ("riscv: clear the instruction cache and all registers when booting") Signed-off-by: Greentime Hu <greentime.hu@sifive.com> --- arch/riscv/kernel/head.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)