| Message ID | 1577428606-69855-4-git-send-email-hanjie.lin@amlogic.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: meson: Add support for USB on Amlogic A1 | expand |
Hi Hanjie, overall this looks good to me and I have one question On Fri, Dec 27, 2019 at 7:37 AM Hanjie Lin <hanjie.lin@amlogic.com> wrote: [...] > + if (priv->soc_id == MESON_SOC_A1) > + value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL; ...here we have some CLK_SEL bit [...] > - priv->clk = devm_clk_get(dev, "xtal"); > - if (IS_ERR(priv->clk)) > - return PTR_ERR(priv->clk); > + if (priv->soc_id == MESON_SOC_G12A) { > + priv->clk = devm_clk_get(dev, "xtal"); > + if (IS_ERR(priv->clk)) > + return PTR_ERR(priv->clk); > + } but here we don't need any parent/input clock? does this mean that the USB2 PHY on the A1 SoC doesn't have any clock inputs? how does it generate the correct clock for itself then? Martin
On Fri, 2019-12-27 at 14:36 +0800, Hanjie Lin wrote: > This adds support for the USB2 PHY found in the Amlogic A1 SoC Family. > > It supports host mode only. > > Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com> > Signed-off-by: Yue Wang <yue.wang@amlogic.com> > --- > drivers/phy/amlogic/phy-meson-g12a-usb2.c | 93 +++++++++++++++++++++---------- > 1 file changed, 64 insertions(+), 29 deletions(-) > > diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c b/drivers/phy/amlogic/phy-meson-g12a-usb2.c > index 9065ffc..a564747 100644 > --- a/drivers/phy/amlogic/phy-meson-g12a-usb2.c > +++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c > @@ -146,11 +146,17 @@ [...] > + priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev); > + > priv->regmap = devm_regmap_init_mmio(dev, base, > &phy_meson_g12a_usb2_regmap_conf); > if (IS_ERR(priv->regmap)) > return PTR_ERR(priv->regmap); > > - priv->clk = devm_clk_get(dev, "xtal"); > - if (IS_ERR(priv->clk)) > - return PTR_ERR(priv->clk); > + if (priv->soc_id == MESON_SOC_G12A) { > + priv->clk = devm_clk_get(dev, "xtal"); > + if (IS_ERR(priv->clk)) > + return PTR_ERR(priv->clk); > + } How about use devm_clk_get_optional(), then make it as optional clock also in dt-binding > >
On 2019/12/28 0:40, Martin Blumenstingl wrote: > Hi Hanjie, > > overall this looks good to me and I have one question > > On Fri, Dec 27, 2019 at 7:37 AM Hanjie Lin <hanjie.lin@amlogic.com> wrote: > [...] >> + if (priv->soc_id == MESON_SOC_A1) >> + value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL; > ...here we have some CLK_SEL bit > > [...] >> - priv->clk = devm_clk_get(dev, "xtal"); >> - if (IS_ERR(priv->clk)) >> - return PTR_ERR(priv->clk); >> + if (priv->soc_id == MESON_SOC_G12A) { >> + priv->clk = devm_clk_get(dev, "xtal"); >> + if (IS_ERR(priv->clk)) >> + return PTR_ERR(priv->clk); >> + } > but here we don't need any parent/input clock? > does this mean that the USB2 PHY on the A1 SoC doesn't have any clock > inputs? how does it generate the correct clock for itself then? > Hi Martin Actually, there is a "xtal_usb_phy" clock in A1 ctrl driver, it seems it's better to be in the A1 phy driver. I will move that clock here in next version. Thanks, Hanjie > > Martin > > _______________________________________________ > linux-amlogic mailing list > linux-amlogic@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-amlogic > > . >
On 2019/12/28 10:53, Chunfeng Yun wrote: > On Fri, 2019-12-27 at 14:36 +0800, Hanjie Lin wrote: >> This adds support for the USB2 PHY found in the Amlogic A1 SoC Family. >> >> It supports host mode only. >> >> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com> >> Signed-off-by: Yue Wang <yue.wang@amlogic.com> >> --- >> drivers/phy/amlogic/phy-meson-g12a-usb2.c | 93 +++++++++++++++++++++---------- >> 1 file changed, 64 insertions(+), 29 deletions(-) >> >> diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c b/drivers/phy/amlogic/phy-meson-g12a-usb2.c >> index 9065ffc..a564747 100644 >> --- a/drivers/phy/amlogic/phy-meson-g12a-usb2.c >> +++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c >> @@ -146,11 +146,17 @@ > [...] >> + priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev); >> + >> priv->regmap = devm_regmap_init_mmio(dev, base, >> &phy_meson_g12a_usb2_regmap_conf); >> if (IS_ERR(priv->regmap)) >> return PTR_ERR(priv->regmap); >> >> - priv->clk = devm_clk_get(dev, "xtal"); >> - if (IS_ERR(priv->clk)) >> - return PTR_ERR(priv->clk); >> + if (priv->soc_id == MESON_SOC_G12A) { >> + priv->clk = devm_clk_get(dev, "xtal"); >> + if (IS_ERR(priv->clk)) >> + return PTR_ERR(priv->clk); >> + } > How about use devm_clk_get_optional(), then make it as optional clock > also in dt-binding >> > >> > Hi Chunfeng Actually, there is a "xtal_usb_phy" clock in A1 ctrl driver, it seems it's better to be in the A1 phy driver. I will move that clock here in next version. Thanks, Hanjie
diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c b/drivers/phy/amlogic/phy-meson-g12a-usb2.c index 9065ffc..a564747 100644 --- a/drivers/phy/amlogic/phy-meson-g12a-usb2.c +++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c @@ -146,11 +146,17 @@ #define RESET_COMPLETE_TIME 1000 #define PLL_RESET_COMPLETE_TIME 100 +enum meson_soc_id { + MESON_SOC_G12A = 0, + MESON_SOC_A1, +}; + struct phy_meson_g12a_usb2_priv { struct device *dev; struct regmap *regmap; struct clk *clk; struct reset_control *reset; + int soc_id; }; static const struct regmap_config phy_meson_g12a_usb2_regmap_conf = { @@ -164,6 +170,7 @@ static int phy_meson_g12a_usb2_init(struct phy *phy) { struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy); int ret; + unsigned int value; ret = reset_control_reset(priv->reset); if (ret) @@ -192,18 +199,22 @@ static int phy_meson_g12a_usb2_init(struct phy *phy) FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) | FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9)); - regmap_write(priv->regmap, PHY_CTRL_R18, - FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) | - FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) | - FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) | - FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) | - FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) | - FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) | - FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) | - FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) | - FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) | - FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) | - PHY_CTRL_R18_MPLL_ACG_RANGE); + value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) | + FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) | + FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) | + FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) | + FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) | + FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) | + FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) | + FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) | + FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) | + FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) | + PHY_CTRL_R18_MPLL_ACG_RANGE; + + if (priv->soc_id == MESON_SOC_A1) + value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL; + + regmap_write(priv->regmap, PHY_CTRL_R18, value); udelay(PLL_RESET_COMPLETE_TIME); @@ -227,13 +238,24 @@ static int phy_meson_g12a_usb2_init(struct phy *phy) FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) | FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0)); - regmap_write(priv->regmap, PHY_CTRL_R4, - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) | - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) | - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) | - PHY_CTRL_R4_TEST_BYPASS_MODE_EN | - FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) | - FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0)); + if (priv->soc_id == MESON_SOC_G12A) + regmap_write(priv->regmap, PHY_CTRL_R4, + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) | + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) | + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) | + PHY_CTRL_R4_TEST_BYPASS_MODE_EN | + FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) | + FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0)); + else if (priv->soc_id == MESON_SOC_A1) { + regmap_write(priv->regmap, PHY_CTRL_R21, + PHY_CTRL_R21_USB2_CAL_ACK_EN | + PHY_CTRL_R21_USB2_TX_STRG_PD | + FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2)); + + /* Analog Settings */ + regmap_write(priv->regmap, PHY_CTRL_R13, + FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7)); + } /* Tuning Disconnect Threshold */ regmap_write(priv->regmap, PHY_CTRL_R3, @@ -241,11 +263,13 @@ static int phy_meson_g12a_usb2_init(struct phy *phy) FIELD_PREP(PHY_CTRL_R3_HSDIC_REF, 1) | FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3)); - /* Analog Settings */ - regmap_write(priv->regmap, PHY_CTRL_R14, 0); - regmap_write(priv->regmap, PHY_CTRL_R13, - PHY_CTRL_R13_UPDATE_PMA_SIGNALS | - FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7)); + if (priv->soc_id == MESON_SOC_G12A) { + /* Analog Settings */ + regmap_write(priv->regmap, PHY_CTRL_R14, 0); + regmap_write(priv->regmap, PHY_CTRL_R13, + PHY_CTRL_R13_UPDATE_PMA_SIGNALS | + FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7)); + } return 0; } @@ -286,14 +310,18 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); + priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev); + priv->regmap = devm_regmap_init_mmio(dev, base, &phy_meson_g12a_usb2_regmap_conf); if (IS_ERR(priv->regmap)) return PTR_ERR(priv->regmap); - priv->clk = devm_clk_get(dev, "xtal"); - if (IS_ERR(priv->clk)) - return PTR_ERR(priv->clk); + if (priv->soc_id == MESON_SOC_G12A) { + priv->clk = devm_clk_get(dev, "xtal"); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + } priv->reset = devm_reset_control_get(dev, "phy"); if (IS_ERR(priv->reset)) @@ -321,8 +349,15 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev) } static const struct of_device_id phy_meson_g12a_usb2_of_match[] = { - { .compatible = "amlogic,g12a-usb2-phy", }, - { }, + { + .compatible = "amlogic,g12a-usb2-phy", + .data = (void *)MESON_SOC_G12A, + }, + { + .compatible = "amlogic,a1-usb2-phy", + .data = (void *)MESON_SOC_A1, + }, + { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, phy_meson_g12a_usb2_of_match);