| Message ID | 20191222141035.1649937-4-thierry.reding@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | memory: tegra: Add Tegra186/Tegra194 support | expand |
On Sun, Dec 22, 2019 at 03:10:25PM +0100, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > The NVIDIA Tegra186 SoC contains a memory subsystem composed of the > memory controller and the external memory controller. The memory > controller provides interfaces for the memory clients to access the > memory. Accesses can be either bounced through the SMMU for IOVA > translation or directly to the EMC. > > The bulk of the programming of the external memory controller happens > through interfaces exposed by the BPMP. Describe this relationship by > adding a phandle reference to the BPMP to the EMC node. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > .../nvidia,tegra186-mc.yaml | 130 ++++++++++++++++++ > 1 file changed, 130 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml > new file mode 100644 > index 000000000000..b98a1d03410b > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml > @@ -0,0 +1,130 @@ > +# SPDX-License-Identifier: (GPL-2.0) Dual license new bindings: (GPL-2.0-only OR BSD-2-Clause) Though maybe this is a copy-n-paste of the other Tegra MC bindings? With that sorted, Reviewed-by: Rob Herring <robh@kernel.org> > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra186 (and later) SoC Memory Controller > + > +maintainers: > + - Jon Hunter <jonathanh@nvidia.com> > + - Thierry Reding <thierry.reding@gmail.com> > + > +description: | > + The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split > + into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC > + handles memory requests for 40-bit virtual addresses from internal clients > + and arbitrates among them to allocate memory bandwidth. > + > + Up to 15 GiB of physical memory can be supported. Security features such as > + encryption of traffic to and from DRAM via general security apertures are > + available for video and other secure applications, as well as DRAM ECC for > + automotive safety applications (single bit error correction and double bit > + error detection). > + > +properties: > + $nodename: > + pattern: "^memory-controller@[0-9a-f]+$" > + > + compatible: > + items: > + - enum: > + - nvidia,tegra186-mc > + - nvidia,tegra194-mc > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 > + > + ranges: true > + > + dma-ranges: true > + > +patternProperties: > + "^external-memory-controller@[0-9a-f]+$": > + description: > + The bulk of the work involved in controlling the external memory > + controller on NVIDIA Tegra186 and later is performed on the BPMP. This > + coprocessor exposes the EMC clock that is used to set the frequency at > + which the external memory is clocked and a remote procedure call that > + can be used to obtain the set of available frequencies. > + type: object > + properties: > + compatible: > + items: > + - enum: > + - nvidia,tegra186-emc > + - nvidia,tegra194-emc > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: external memory clock > + > + clock-names: > + items: > + - const: emc > + > + nvidia,bpmp: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + phandle of the node representing the BPMP > + > +required: > + - compatible > + - reg > + - interrupts > + - "#address-cells" > + - "#size-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/tegra186-clock.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + memory-controller@2c00000 { > + compatible = "nvidia,tegra186-mc"; > + reg = <0x0 0x02c00000 0x0 0xb0000>; > + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + ranges = <0x0 0x02c00000 0x02c00000 0x0 0xb0000>; > + > + /* > + * Memory clients have access to all 40 bits that the memory > + * controller can address. > + */ > + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; > + > + external-memory-controller@2c60000 { > + compatible = "nvidia,tegra186-emc"; > + reg = <0x0 0x02c60000 0x0 0x50000>; > + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&bpmp TEGRA186_CLK_EMC>; > + clock-names = "emc"; > + > + nvidia,bpmp = <&bpmp>; > + }; > + }; > + > + bpmp: bpmp { > + compatible = "nvidia,tegra186-bpmp"; > + #clock-cells = <1>; > + }; > -- > 2.24.1 >
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml new file mode 100644 index 000000000000..b98a1d03410b --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 (and later) SoC Memory Controller + +maintainers: + - Jon Hunter <jonathanh@nvidia.com> + - Thierry Reding <thierry.reding@gmail.com> + +description: | + The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split + into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC + handles memory requests for 40-bit virtual addresses from internal clients + and arbitrates among them to allocate memory bandwidth. + + Up to 15 GiB of physical memory can be supported. Security features such as + encryption of traffic to and from DRAM via general security apertures are + available for video and other secure applications, as well as DRAM ECC for + automotive safety applications (single bit error correction and double bit + error detection). + +properties: + $nodename: + pattern: "^memory-controller@[0-9a-f]+$" + + compatible: + items: + - enum: + - nvidia,tegra186-mc + - nvidia,tegra194-mc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + dma-ranges: true + +patternProperties: + "^external-memory-controller@[0-9a-f]+$": + description: + The bulk of the work involved in controlling the external memory + controller on NVIDIA Tegra186 and later is performed on the BPMP. This + coprocessor exposes the EMC clock that is used to set the frequency at + which the external memory is clocked and a remote procedure call that + can be used to obtain the set of available frequencies. + type: object + properties: + compatible: + items: + - enum: + - nvidia,tegra186-emc + - nvidia,tegra194-emc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: external memory clock + + clock-names: + items: + - const: emc + + nvidia,bpmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of the node representing the BPMP + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra186-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + memory-controller@2c00000 { + compatible = "nvidia,tegra186-mc"; + reg = <0x0 0x02c00000 0x0 0xb0000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x02c00000 0x02c00000 0x0 0xb0000>; + + /* + * Memory clients have access to all 40 bits that the memory + * controller can address. + */ + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + + external-memory-controller@2c60000 { + compatible = "nvidia,tegra186-emc"; + reg = <0x0 0x02c60000 0x0 0x50000>; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA186_CLK_EMC>; + clock-names = "emc"; + + nvidia,bpmp = <&bpmp>; + }; + }; + + bpmp: bpmp { + compatible = "nvidia,tegra186-bpmp"; + #clock-cells = <1>; + };