| Message ID | 20191230074102.50982-1-vadivel.muruganx.ramuthevar@linux.intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | spi: cadence-quadpsi: Add support for the Cadence QSPI controller | expand |
Hi, On 12/30/2019 1:11 PM, Ramuthevar,Vadivel MuruganX wrote: > Add support for the Cadence QSPI controller. This controller is > present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs. > This driver has been tested on the Intel LGM SoCs. > > This driver does not support generic SPI and also the implementation > only supports spi-mem interface to replace the existing driver in > mtd/spi-nor/cadence-quadspi.c, the existing driver only support SPI-NOR > flash memory. > I am finally able to get spi-mem based cadence-quaspi driver working on TI platforms with DMA and DAC mode. I have also incorporated changes to disable DAC and autopolling for your intel SoC: https://github.com/r-vignesh/linux/commits/qspi (Top two patches are of interest) I have tested both DAC and INDAC mode with s25fl flash and everything seems to be fine. Could you re test the driver on your SoC? Feel free to fold it into your series if everything works. Regards Vignesh
Hi, On 15/1/2020 2:13 PM, Vignesh Raghavendra wrote: > Hi, > > On 12/30/2019 1:11 PM, Ramuthevar,Vadivel MuruganX wrote: >> Add support for the Cadence QSPI controller. This controller is >> present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs. >> This driver has been tested on the Intel LGM SoCs. >> >> This driver does not support generic SPI and also the implementation >> only supports spi-mem interface to replace the existing driver in >> mtd/spi-nor/cadence-quadspi.c, the existing driver only support SPI-NOR >> flash memory. >> > > > I am finally able to get spi-mem based cadence-quaspi driver working on > TI platforms with DMA and DAC mode. I have also incorporated changes to > disable DAC and autopolling for your intel SoC: Thanks! a lot for the confirmation, with your changes it is working on TI platform. > https://github.com/r-vignesh/linux/commits/qspi > > (Top two patches are of interest) > > I have tested both DAC and INDAC mode with s25fl flash and everything > seems to be fine. Could you re test the driver on your SoC? Feel free to > fold it into your series if everything works. sure, I will test on Intel SoC with your changes . Regards Vadivel > Regards > Vignesh > > >
Hi, On 15/1/2020 2:21 PM, Ramuthevar, Vadivel MuruganX wrote: > Hi, > > On 15/1/2020 2:13 PM, Vignesh Raghavendra wrote: >> Hi, >> >> On 12/30/2019 1:11 PM, Ramuthevar,Vadivel MuruganX wrote: >>> Add support for the Cadence QSPI controller. This controller is >>> present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs. >>> This driver has been tested on the Intel LGM SoCs. >>> >>> This driver does not support generic SPI and also the implementation >>> only supports spi-mem interface to replace the existing driver in >>> mtd/spi-nor/cadence-quadspi.c, the existing driver only support SPI-NOR >>> flash memory. >>> >> >> >> I am finally able to get spi-mem based cadence-quaspi driver working on >> TI platforms with DMA and DAC mode. I have also incorporated changes to >> disable DAC and autopolling for your intel SoC: > > Thanks! a lot for the confirmation, with your changes it is working on > TI platform. > >> https://github.com/r-vignesh/linux/commits/qspi >> >> (Top two patches are of interest) >> >> I have tested both DAC and INDAC mode with s25fl flash and everything >> seems to be fine. Could you re test the driver on your SoC? while re-testing QSPI_NOR/NAND both didn't work, after few changes from patchV6 followed by your changes, now QSPI-NOR started working, soon will be sending updated patch version which includes your changes as well as my changes without affecting both the platforms(TI and Intel). BTW, Have you tested QSPI-NAND on your platform ? with our patches. Thanks! for your review and support. Regards Vadivel >> Feel free to >> fold it into your series if everything works. > sure, I will test on Intel SoC with your changes . > > Regards > Vadivel >> Regards >> Vignesh >> >> >>
Hi Vignesh, > -----Original Message----- > From: linux-kernel-owner@vger.kernel.org <linux-kernel- > owner@vger.kernel.org> On Behalf Of Vignesh Raghavendra > Sent: Wednesday, January 15, 2020 11:43 AM > To: Ramuthevar,Vadivel MuruganX > <vadivel.muruganx.ramuthevar@linux.intel.com>; broonie@kernel.org; linux- > spi@vger.kernel.org; linux-kernel@vger.kernel.org > Cc: robh+dt@kernel.org; dan.carpenter@oracle.com; > cheol.yong.kim@intel.com; qi-ming.wu@intel.com > Subject: [EXT] Re: [PATCH v6 0/2] spi: cadence-quadpsi: Add support for the > Cadence QSPI controller > > Caution: EXT Email > > Hi, > > On 12/30/2019 1:11 PM, Ramuthevar,Vadivel MuruganX wrote: > > Add support for the Cadence QSPI controller. This controller is > > present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs. > > This driver has been tested on the Intel LGM SoCs. > > > > This driver does not support generic SPI and also the implementation > > only supports spi-mem interface to replace the existing driver in > > mtd/spi-nor/cadence-quadspi.c, the existing driver only support > > SPI-NOR flash memory. > > > > > > I am finally able to get spi-mem based cadence-quaspi driver working on TI > platforms with DMA and DAC mode. I have also incorporated changes to > disable DAC and autopolling for your intel SoC: > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.co > m%2Fr- > vignesh%2Flinux%2Fcommits%2Fqspi&data=02%7C01%7Ckuldeep.singh% > 40nxp.com%7Ccbd14ac527ae4298a28808d7998219e6%7C686ea1d3bc2b4c6fa > 92cd99c5c301635%7C0%7C0%7C637146656365872638&sdata=jAR7lmry > R9fdqF3e4A2dQzF0Q0fYxMvM7sNhx8lvoy0%3D&reserved=0 > > (Top two patches are of interest) > > I have tested both DAC and INDAC mode with s25fl flash and everything seems > to be fine. Could you re test the driver on your SoC? Feel free to fold it into > your series if everything works. Is JFFS2/UBIFS a valid use case here? And were you able to test the same? I see few issues with Spansion flashes (s25fs) in framework and couldn’t make FS utilities run. On the other hand, file systems on other flashes (ex: micron, mt25qu) are showing positive results. Thanks Kuldeep > > Regards > Vignesh > >
On 23/01/20 12:54 pm, Kuldeep Singh wrote: > Hi Vignesh, > >> -----Original Message----- >> From: linux-kernel-owner@vger.kernel.org <linux-kernel- >> owner@vger.kernel.org> On Behalf Of Vignesh Raghavendra >> Sent: Wednesday, January 15, 2020 11:43 AM >> To: Ramuthevar,Vadivel MuruganX >> <vadivel.muruganx.ramuthevar@linux.intel.com>; broonie@kernel.org; linux- >> spi@vger.kernel.org; linux-kernel@vger.kernel.org >> Cc: robh+dt@kernel.org; dan.carpenter@oracle.com; >> cheol.yong.kim@intel.com; qi-ming.wu@intel.com >> Subject: [EXT] Re: [PATCH v6 0/2] spi: cadence-quadpsi: Add support for the >> Cadence QSPI controller >> >> Caution: EXT Email >> >> Hi, >> >> On 12/30/2019 1:11 PM, Ramuthevar,Vadivel MuruganX wrote: >>> Add support for the Cadence QSPI controller. This controller is >>> present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs. >>> This driver has been tested on the Intel LGM SoCs. >>> >>> This driver does not support generic SPI and also the implementation >>> only supports spi-mem interface to replace the existing driver in >>> mtd/spi-nor/cadence-quadspi.c, the existing driver only support >>> SPI-NOR flash memory. >>> >> >> >> >> I am finally able to get spi-mem based cadence-quaspi driver working on TI >> platforms with DMA and DAC mode. I have also incorporated changes to >> disable DAC and autopolling for your intel SoC: >> >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.co >> m%2Fr- >> vignesh%2Flinux%2Fcommits%2Fqspi&data=02%7C01%7Ckuldeep.singh% >> 40nxp.com%7Ccbd14ac527ae4298a28808d7998219e6%7C686ea1d3bc2b4c6fa >> 92cd99c5c301635%7C0%7C0%7C637146656365872638&sdata=jAR7lmry >> R9fdqF3e4A2dQzF0Q0fYxMvM7sNhx8lvoy0%3D&reserved=0 >> >> (Top two patches are of interest) >> >> I have tested both DAC and INDAC mode with s25fl flash and everything seems >> to be fine. Could you re test the driver on your SoC? Feel free to fold it into >> your series if everything works. > > Is JFFS2/UBIFS a valid use case here? And were you able to test the same? > I see few issues with Spansion flashes (s25fs) in framework and couldn’t make FS utilities run. > On the other hand, file systems on other flashes (ex: micron, mt25qu) are showing positive results. > I did test with s25fl512s with UBIFS and did not see any issue. Could you try with latest linux master or linux next? There were couple of fixes in the last -rc related to spansion flashes? [1] https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git/commit/?h=mtd/fixes&id=440b6d50254bdbd84c2a665c7f53ec69dd741a4f [2]https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git/commit/?h=mtd/fixes&id=da2ef8124f20b4ce18d1d3d24fc7b88e687e10bb > Thanks > Kuldeep > >> >> Regards >> Vignesh >> >> >
On 21/01/20 5:17 pm, Ramuthevar, Vadivel MuruganX wrote: > Hi, > > On 15/1/2020 2:21 PM, Ramuthevar, Vadivel MuruganX wrote: >> Hi, >> >> On 15/1/2020 2:13 PM, Vignesh Raghavendra wrote: >>> Hi, >>> >>> On 12/30/2019 1:11 PM, Ramuthevar,Vadivel MuruganX wrote: >>>> Add support for the Cadence QSPI controller. This controller is >>>> present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs. >>>> This driver has been tested on the Intel LGM SoCs. >>>> >>>> This driver does not support generic SPI and also the implementation >>>> only supports spi-mem interface to replace the existing driver in >>>> mtd/spi-nor/cadence-quadspi.c, the existing driver only support SPI-NOR >>>> flash memory. >>>> >>> >>> >>> I am finally able to get spi-mem based cadence-quaspi driver working on >>> TI platforms with DMA and DAC mode. I have also incorporated changes to >>> disable DAC and autopolling for your intel SoC: >> >> Thanks! a lot for the confirmation, with your changes it is working on >> TI platform. >> >>> https://github.com/r-vignesh/linux/commits/qspi >>> >>> (Top two patches are of interest) >>> >>> I have tested both DAC and INDAC mode with s25fl flash and everything >>> seems to be fine. Could you re test the driver on your SoC? > > while re-testing QSPI_NOR/NAND both didn't work, after few changes from > patchV6 followed by your changes, > > now QSPI-NOR started working, soon will be sending updated patch > version which includes your changes as well as my changes > > without affecting both the platforms(TI and Intel). > > BTW, Have you tested QSPI-NAND on your platform ? with our patches. No, I don't have a platform with QSPI-NAND. Regards Vignesh
Hi Vignesh, > -----Original Message----- > From: Vignesh Raghavendra <vigneshr@ti.com> > Sent: Thursday, January 23, 2020 1:17 PM > To: Kuldeep Singh <kuldeep.singh@nxp.com>; Ramuthevar,Vadivel MuruganX > <vadivel.muruganx.ramuthevar@linux.intel.com>; broonie@kernel.org; linux- > spi@vger.kernel.org; linux-kernel@vger.kernel.org > Cc: robh+dt@kernel.org; dan.carpenter@oracle.com; > cheol.yong.kim@intel.com; qi-ming.wu@intel.com > Subject: Re: [EXT] Re: [PATCH v6 0/2] spi: cadence-quadpsi: Add support for > the Cadence QSPI controller > > Caution: EXT Email > > On 23/01/20 12:54 pm, Kuldeep Singh wrote: > > Hi Vignesh, > > > >> -----Original Message----- > >> From: linux-kernel-owner@vger.kernel.org <linux-kernel- > >> owner@vger.kernel.org> On Behalf Of Vignesh Raghavendra > >> Sent: Wednesday, January 15, 2020 11:43 AM > >> To: Ramuthevar,Vadivel MuruganX > >> <vadivel.muruganx.ramuthevar@linux.intel.com>; broonie@kernel.org; > >> linux- spi@vger.kernel.org; linux-kernel@vger.kernel.org > >> Cc: robh+dt@kernel.org; dan.carpenter@oracle.com; > >> cheol.yong.kim@intel.com; qi-ming.wu@intel.com > >> Subject: [EXT] Re: [PATCH v6 0/2] spi: cadence-quadpsi: Add support > >> for the Cadence QSPI controller > >> > >> Caution: EXT Email > >> > >> Hi, > >> > >> On 12/30/2019 1:11 PM, Ramuthevar,Vadivel MuruganX wrote: > >>> Add support for the Cadence QSPI controller. This controller is > >>> present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs. > >>> This driver has been tested on the Intel LGM SoCs. > >>> > >>> This driver does not support generic SPI and also the implementation > >>> only supports spi-mem interface to replace the existing driver in > >>> mtd/spi-nor/cadence-quadspi.c, the existing driver only support > >>> SPI-NOR flash memory. > >>> > >> > >> > >> > >> I am finally able to get spi-mem based cadence-quaspi driver working > >> on TI platforms with DMA and DAC mode. I have also incorporated > >> changes to disable DAC and autopolling for your intel SoC: > >> > >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit > >> hub.co > >> m%2Fr- > >> > vignesh%2Flinux%2Fcommits%2Fqspi&data=02%7C01%7Ckuldeep.singh% > >> > 40nxp.com%7Ccbd14ac527ae4298a28808d7998219e6%7C686ea1d3bc2b4c6fa > >> > 92cd99c5c301635%7C0%7C0%7C637146656365872638&sdata=jAR7lmry > >> R9fdqF3e4A2dQzF0Q0fYxMvM7sNhx8lvoy0%3D&reserved=0 > >> > >> (Top two patches are of interest) > >> > >> I have tested both DAC and INDAC mode with s25fl flash and everything > >> seems to be fine. Could you re test the driver on your SoC? Feel free > >> to fold it into your series if everything works. > > > > Is JFFS2/UBIFS a valid use case here? And were you able to test the same? > > I see few issues with Spansion flashes (s25fs) in framework and couldn’t > make FS utilities run. > > On the other hand, file systems on other flashes (ex: micron, mt25qu) are > showing positive results. > > > > I did test with s25fl512s with UBIFS and did not see any issue. Thanks Vignesh for this confirmation. >Could you try with latest linux master or linux next? There were couple of fixes in the last -rc > related to spansion flashes? Yes, I have already applied those patches and still facing this issue. I am testing with s25fs512s and only able to make it work on 1bit mode and that too by skipping SFDP. Basic read/write works on other modes but not FS utilities. Could you please share any pointer to look into which direction. Thanks in advance. Thanks Kuldeep > > [1] > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kerne > l.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fmtd%2Flinux.git%2Fcommit > %2F%3Fh%3Dmtd%2Ffixes%26id%3D440b6d50254bdbd84c2a665c7f53ec69dd > 741a4f&data=02%7C01%7Ckuldeep.singh%40nxp.com%7Cee345bdf9f654 > 4ac9f4508d79fd863d9%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7 > C637153624041330774&sdata=OyKGl2jn5JDq5KCaVrxAnUh4qSynmAhS% > 2FeFiOxJSKtU%3D&reserved=0 > [2]https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.ker > nel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fmtd%2Flinux.git%2Fcomm > it%2F%3Fh%3Dmtd%2Ffixes%26id%3Dda2ef8124f20b4ce18d1d3d24fc7b88e68 > 7e10bb&data=02%7C01%7Ckuldeep.singh%40nxp.com%7Cee345bdf9f65 > 44ac9f4508d79fd863d9%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0% > 7C637153624041330774&sdata=BTRzWWY2z6nZncyktDDIdJFwYTp41S%2 > Buh99QaJ60e1M%3D&reserved=0 > > > Thanks > > Kuldeep > > > >> > >> Regards > >> Vignesh > >> > >> > > > > -- > Regards > Vignesh
Hi, On 23/01/20 5:07 pm, Kuldeep Singh wrote: > Hi Vignesh, > [...] >> I did test with s25fl512s with UBIFS and did not see any issue. > > Thanks Vignesh for this confirmation. > >> Could you try with latest linux master or linux next? There were couple of fixes in the last -rc >> related to spansion flashes? > > Yes, I have already applied those patches and still facing this issue. > I am testing with s25fs512s and only able to make it work on 1bit mode and that too by skipping SFDP. Hmm, why would you need to skip SFDP parsing in 1 bit mode? What actually fails when SFDP is parsed? Read/write/erase? BTW, did s25fs512s flash ever with you controller before (i.e is this a regression)? > Basic read/write works on other modes but not FS utilities. > Could you please share any pointer to look into which direction. Thanks in advance. > If 1 bit mode works fine, then probably flash FS in 1 bit mode and they try read only mount in quad mode. Thus try and narrow down if the issue is in read path vs write path. Regards Vignesh > Thanks > Kuldeep > >> >> [1] >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kerne >> l.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fmtd%2Flinux.git%2Fcommit >> %2F%3Fh%3Dmtd%2Ffixes%26id%3D440b6d50254bdbd84c2a665c7f53ec69dd >> 741a4f&data=02%7C01%7Ckuldeep.singh%40nxp.com%7Cee345bdf9f654 >> 4ac9f4508d79fd863d9%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7 >> C637153624041330774&sdata=OyKGl2jn5JDq5KCaVrxAnUh4qSynmAhS% >> 2FeFiOxJSKtU%3D&reserved=0 >> [2]https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.ker >> nel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fmtd%2Flinux.git%2Fcomm >> it%2F%3Fh%3Dmtd%2Ffixes%26id%3Dda2ef8124f20b4ce18d1d3d24fc7b88e68 >> 7e10bb&data=02%7C01%7Ckuldeep.singh%40nxp.com%7Cee345bdf9f65 >> 44ac9f4508d79fd863d9%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0% >> 7C637153624041330774&sdata=BTRzWWY2z6nZncyktDDIdJFwYTp41S%2 >> Buh99QaJ60e1M%3D&reserved=0 >> >>> Thanks >>> Kuldeep >>> >>>> >>>> Regards >>>> Vignesh >>>> >>>> >>> >> >> -- >> Regards >> Vignesh
Add support for the Cadence QSPI controller. This controller is present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs. This driver has been tested on the Intel LGM SoCs. This driver does not support generic SPI and also the implementation only supports spi-mem interface to replace the existing driver in mtd/spi-nor/cadence-quadspi.c, the existing driver only support SPI-NOR flash memory. Thank you Vignesh for the valuable review comments and guidance, sorry for the delay since waitting for the merge window to rebase and send it now by one-shot. changes from v5: -- kbuild test robot warnings fixed -- Add Reported-By: Dan Carpenter <dan.carpenter@oracle.com> changes from v4: -- kbuild test robot warnings fixed -- Add Reborted-by: tag changes from v3: spi-cadence-quadspi.c -- static to all functions wrt to local to the file. -- Prefix cqspi_ and make the function static -- cmd_ops, data_ops and dummy_ops dropped -- addr_ops kept since it is required for address calculation. -- devm_ used for supported functions , removed legacy API's -- removed "indirect" name from functions -- replaced by master->mode_bits = SPI_RX_QUAD | SPI_TX_DUAL | SPI_RX_DUAL | SPI_RX_OCTAL; as per Vignesh susggestion -- removed free functions since devm_ handles automatically. -- dropped all unused Macros YAML file update: -- cadence,qspi.yaml file name replace by cdns,qspi-nor.yaml -- compatible string updated as per Vignesh suggestion -- for single entry, removed descriptions -- removed optional parameters Build Result: linux$ make DT_SCHEMA_FILES=Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml dt_binding_check CHKDT Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml SCHEMA Documentation/devicetree/bindings/processed-schema.yaml DTC Documentation/devicetree/bindings/spi/cdns,qspi-nor.example.dt.yaml CHECK Documentation/devicetree/bindings/spi/cdns,qspi-nor.example.dt.yaml Ramuthevar Vadivel Murugan (2): dt-bindings: spi: Add schema for Cadence QSPI Controller driver spi: cadence-quadpsi: Add support for the Cadence QSPI controller .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 147 +++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/spi-cadence-quadspi.c | 1175 ++++++++++++++++++++ drivers/spi/spi-cadence-quadspi.h | 245 ++++ 5 files changed, 1576 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml create mode 100644 drivers/spi/spi-cadence-quadspi.c create mode 100644 drivers/spi/spi-cadence-quadspi.h base-commit: c52db0e2f5ec0e5e196fe0045621dcb0141bf90f