| Message ID | 20200127103652.2326-1-alexandru.elisei@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: arm64: Treat emulated TVAL TimerValue as a signed 32-bit integer | expand |
Hi Alexandru, On 2020-01-27 10:36, Alexandru Elisei wrote: > According to the ARM ARM, registers CNT{P,V}_TVAL_EL0 have bits [63:32] > RES0 [1]. When reading the register, the value is truncated to the > least > significant 32 bits [2], and on writes, TimerValue is treated as a > signed > 32-bit integer [1, 2]. > > When the guest behaves correctly and writes 32-bit values, treating > TVAL > as an unsigned 64 bit register works as expected. However, things start > to break down when the guest writes larger values, because > (u64)0x1_ffff_ffff = 8589934591. but (s32)0x1_ffff_ffff = -1, and the > former will cause the timer interrupt to be asserted in the future, but > the latter will cause it to be asserted now. Let's treat TVAL as a > signed 32-bit register on writes, to match the behaviour described in > the architecture, and the behaviour experimentally exhibited by the > virtual timer on a non-vhe host. > > [1] Arm DDI 0487E.a, section D13.8.18 > [2] Arm DDI 0487E.a, section D11.2.4 > > Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Huhuh... Nice catch! Fixes: 8fa761624871 ("KVM: arm/arm64: arch_timer: Fix CNTP_TVAL calculation") (how many times are we doing to fix this???) > --- > include/kvm/arm_arch_timer.h | 2 ++ > virt/kvm/arm/arch_timer.c | 3 ++- > 2 files changed, 4 insertions(+), 1 deletion(-) > > diff --git a/include/kvm/arm_arch_timer.h > b/include/kvm/arm_arch_timer.h > index d120e6c323e7..be912176b7a3 100644 > --- a/include/kvm/arm_arch_timer.h > +++ b/include/kvm/arm_arch_timer.h > @@ -10,6 +10,8 @@ > #include <linux/clocksource.h> > #include <linux/hrtimer.h> > > +#define ARCH_TIMER_TVAL_MASK ((1ULL << 32) - 1) > + > enum kvm_arch_timers { > TIMER_PTIMER, > TIMER_VTIMER, > diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c > index f182b2380345..5d40f17f7024 100644 > --- a/virt/kvm/arm/arch_timer.c > +++ b/virt/kvm/arm/arch_timer.c > @@ -805,6 +805,7 @@ static u64 kvm_arm_timer_read(struct kvm_vcpu > *vcpu, > switch (treg) { > case TIMER_REG_TVAL: > val = timer->cnt_cval - kvm_phys_timer_read() + timer->cntvoff; > + val &= ARCH_TIMER_TVAL_MASK; nit: Do we really need this mask? I'd rather see it written as val = lower_32_bits(val); > break; > > case TIMER_REG_CTL: > @@ -850,7 +851,7 @@ static void kvm_arm_timer_write(struct kvm_vcpu > *vcpu, > { > switch (treg) { > case TIMER_REG_TVAL: > - timer->cnt_cval = kvm_phys_timer_read() - timer->cntvoff + val; > + timer->cnt_cval = kvm_phys_timer_read() - timer->cntvoff + (s32)val; > break; > > case TIMER_REG_CTL: Otherwise, looks good to me. If you're OK with the above change, I'll take it as a fix. Thanks, M.
Hi, On 1/27/20 11:07 AM, Marc Zyngier wrote: > Hi Alexandru, > > On 2020-01-27 10:36, Alexandru Elisei wrote: >> According to the ARM ARM, registers CNT{P,V}_TVAL_EL0 have bits [63:32] >> RES0 [1]. When reading the register, the value is truncated to the least >> significant 32 bits [2], and on writes, TimerValue is treated as a signed >> 32-bit integer [1, 2]. >> >> When the guest behaves correctly and writes 32-bit values, treating TVAL >> as an unsigned 64 bit register works as expected. However, things start >> to break down when the guest writes larger values, because >> (u64)0x1_ffff_ffff = 8589934591. but (s32)0x1_ffff_ffff = -1, and the >> former will cause the timer interrupt to be asserted in the future, but >> the latter will cause it to be asserted now. Let's treat TVAL as a >> signed 32-bit register on writes, to match the behaviour described in >> the architecture, and the behaviour experimentally exhibited by the >> virtual timer on a non-vhe host. >> >> [1] Arm DDI 0487E.a, section D13.8.18 >> [2] Arm DDI 0487E.a, section D11.2.4 >> >> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> > > Huhuh... Nice catch! > > Fixes: 8fa761624871 ("KVM: arm/arm64: arch_timer: Fix CNTP_TVAL calculation") > > (how many times are we doing to fix this???) > >> --- >> include/kvm/arm_arch_timer.h | 2 ++ >> virt/kvm/arm/arch_timer.c | 3 ++- >> 2 files changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h >> index d120e6c323e7..be912176b7a3 100644 >> --- a/include/kvm/arm_arch_timer.h >> +++ b/include/kvm/arm_arch_timer.h >> @@ -10,6 +10,8 @@ >> #include <linux/clocksource.h> >> #include <linux/hrtimer.h> >> >> +#define ARCH_TIMER_TVAL_MASK ((1ULL << 32) - 1) >> + >> enum kvm_arch_timers { >> TIMER_PTIMER, >> TIMER_VTIMER, >> diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c >> index f182b2380345..5d40f17f7024 100644 >> --- a/virt/kvm/arm/arch_timer.c >> +++ b/virt/kvm/arm/arch_timer.c >> @@ -805,6 +805,7 @@ static u64 kvm_arm_timer_read(struct kvm_vcpu *vcpu, >> switch (treg) { >> case TIMER_REG_TVAL: >> val = timer->cnt_cval - kvm_phys_timer_read() + timer->cntvoff; >> + val &= ARCH_TIMER_TVAL_MASK; > > nit: Do we really need this mask? I'd rather see it written as > > val = lower_32_bits(val); I didn't really like using the mask either, but I couldn't think of anything better. This looks very good. > > >> break; >> >> case TIMER_REG_CTL: >> @@ -850,7 +851,7 @@ static void kvm_arm_timer_write(struct kvm_vcpu *vcpu, >> { >> switch (treg) { >> case TIMER_REG_TVAL: >> - timer->cnt_cval = kvm_phys_timer_read() - timer->cntvoff + val; >> + timer->cnt_cval = kvm_phys_timer_read() - timer->cntvoff + (s32)val; >> break; >> >> case TIMER_REG_CTL: > > Otherwise, looks good to me. If you're OK with the above change, I'll > take it as a fix. Yes, I'm very much OK with the change. Thanks, Alex > > Thanks, > > M.
diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index d120e6c323e7..be912176b7a3 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -10,6 +10,8 @@ #include <linux/clocksource.h> #include <linux/hrtimer.h> +#define ARCH_TIMER_TVAL_MASK ((1ULL << 32) - 1) + enum kvm_arch_timers { TIMER_PTIMER, TIMER_VTIMER, diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index f182b2380345..5d40f17f7024 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -805,6 +805,7 @@ static u64 kvm_arm_timer_read(struct kvm_vcpu *vcpu, switch (treg) { case TIMER_REG_TVAL: val = timer->cnt_cval - kvm_phys_timer_read() + timer->cntvoff; + val &= ARCH_TIMER_TVAL_MASK; break; case TIMER_REG_CTL: @@ -850,7 +851,7 @@ static void kvm_arm_timer_write(struct kvm_vcpu *vcpu, { switch (treg) { case TIMER_REG_TVAL: - timer->cnt_cval = kvm_phys_timer_read() - timer->cntvoff + val; + timer->cnt_cval = kvm_phys_timer_read() - timer->cntvoff + (s32)val; break; case TIMER_REG_CTL:
According to the ARM ARM, registers CNT{P,V}_TVAL_EL0 have bits [63:32] RES0 [1]. When reading the register, the value is truncated to the least significant 32 bits [2], and on writes, TimerValue is treated as a signed 32-bit integer [1, 2]. When the guest behaves correctly and writes 32-bit values, treating TVAL as an unsigned 64 bit register works as expected. However, things start to break down when the guest writes larger values, because (u64)0x1_ffff_ffff = 8589934591. but (s32)0x1_ffff_ffff = -1, and the former will cause the timer interrupt to be asserted in the future, but the latter will cause it to be asserted now. Let's treat TVAL as a signed 32-bit register on writes, to match the behaviour described in the architecture, and the behaviour experimentally exhibited by the virtual timer on a non-vhe host. [1] Arm DDI 0487E.a, section D13.8.18 [2] Arm DDI 0487E.a, section D11.2.4 Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> --- include/kvm/arm_arch_timer.h | 2 ++ virt/kvm/arm/arch_timer.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-)