| Message ID | 20200130132558.10201-24-maz@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/23] KVM: arm64: Only sign-extend MMIO up to register width | expand |
Hi, On 1/30/20 1:25 PM, Marc Zyngier wrote: > From: Alexandru Elisei <alexandru.elisei@arm.com> > > According to the ARM ARM, registers CNT{P,V}_TVAL_EL0 have bits [63:32] > RES0 [1]. When reading the register, the value is truncated to the least > significant 32 bits [2], and on writes, TimerValue is treated as a signed > 32-bit integer [1, 2]. > > When the guest behaves correctly and writes 32-bit values, treating TVAL > as an unsigned 64 bit register works as expected. However, things start > to break down when the guest writes larger values, because > (u64)0x1_ffff_ffff = 8589934591. but (s32)0x1_ffff_ffff = -1, and the > former will cause the timer interrupt to be asserted in the future, but > the latter will cause it to be asserted now. Let's treat TVAL as a > signed 32-bit register on writes, to match the behaviour described in > the architecture, and the behaviour experimentally exhibited by the > virtual timer on a non-vhe host. > > [1] Arm DDI 0487E.a, section D13.8.18 > [2] Arm DDI 0487E.a, section D11.2.4 > > Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> > [maz: replaced the read-side mask with lower_32_bits] > Signed-off-by: Marc Zyngier <maz@kernel.org> > Fixes: 8fa761624871 ("KVM: arm/arm64: arch_timer: Fix CNTP_TVAL calculation") > Link: https://lore.kernel.org/r/20200127103652.2326-1-alexandru.elisei@arm.com > --- > virt/kvm/arm/arch_timer.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c > index f182b2380345..c6c2a9dde00c 100644 > --- a/virt/kvm/arm/arch_timer.c > +++ b/virt/kvm/arm/arch_timer.c > @@ -805,6 +805,7 @@ static u64 kvm_arm_timer_read(struct kvm_vcpu *vcpu, > switch (treg) { > case TIMER_REG_TVAL: > val = timer->cnt_cval - kvm_phys_timer_read() + timer->cntvoff; > + val &= lower_32_bits(val); This is correct, but how about making it val = lower_32_bits(val) for more clarity? Apologies for not spotting it earlier :( Thanks, Alex > break; > > case TIMER_REG_CTL: > @@ -850,7 +851,7 @@ static void kvm_arm_timer_write(struct kvm_vcpu *vcpu, > { > switch (treg) { > case TIMER_REG_TVAL: > - timer->cnt_cval = kvm_phys_timer_read() - timer->cntvoff + val; > + timer->cnt_cval = kvm_phys_timer_read() - timer->cntvoff + (s32)val; > break; > > case TIMER_REG_CTL:
On 2020-01-30 14:11, Alexandru Elisei wrote: > Hi, > > On 1/30/20 1:25 PM, Marc Zyngier wrote: >> From: Alexandru Elisei <alexandru.elisei@arm.com> >> >> According to the ARM ARM, registers CNT{P,V}_TVAL_EL0 have bits >> [63:32] >> RES0 [1]. When reading the register, the value is truncated to the >> least >> significant 32 bits [2], and on writes, TimerValue is treated as a >> signed >> 32-bit integer [1, 2]. >> >> When the guest behaves correctly and writes 32-bit values, treating >> TVAL >> as an unsigned 64 bit register works as expected. However, things >> start >> to break down when the guest writes larger values, because >> (u64)0x1_ffff_ffff = 8589934591. but (s32)0x1_ffff_ffff = -1, and the >> former will cause the timer interrupt to be asserted in the future, >> but >> the latter will cause it to be asserted now. Let's treat TVAL as a >> signed 32-bit register on writes, to match the behaviour described in >> the architecture, and the behaviour experimentally exhibited by the >> virtual timer on a non-vhe host. >> >> [1] Arm DDI 0487E.a, section D13.8.18 >> [2] Arm DDI 0487E.a, section D11.2.4 >> >> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> >> [maz: replaced the read-side mask with lower_32_bits] >> Signed-off-by: Marc Zyngier <maz@kernel.org> >> Fixes: 8fa761624871 ("KVM: arm/arm64: arch_timer: Fix CNTP_TVAL >> calculation") >> Link: >> https://lore.kernel.org/r/20200127103652.2326-1-alexandru.elisei@arm.com >> --- >> virt/kvm/arm/arch_timer.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c >> index f182b2380345..c6c2a9dde00c 100644 >> --- a/virt/kvm/arm/arch_timer.c >> +++ b/virt/kvm/arm/arch_timer.c >> @@ -805,6 +805,7 @@ static u64 kvm_arm_timer_read(struct kvm_vcpu >> *vcpu, >> switch (treg) { >> case TIMER_REG_TVAL: >> val = timer->cnt_cval - kvm_phys_timer_read() + timer->cntvoff; >> + val &= lower_32_bits(val); > > This is correct, but how about making it val = lower_32_bits(val) for > more > clarity? Apologies for not spotting it earlier :( That's what it should have been, but I obviously typoed it. As it passed all my tests, I didn't notice the issue. I'll queue a cleanup once Paolo has a chance to pull this. M.
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index f182b2380345..c6c2a9dde00c 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -805,6 +805,7 @@ static u64 kvm_arm_timer_read(struct kvm_vcpu *vcpu, switch (treg) { case TIMER_REG_TVAL: val = timer->cnt_cval - kvm_phys_timer_read() + timer->cntvoff; + val &= lower_32_bits(val); break; case TIMER_REG_CTL: @@ -850,7 +851,7 @@ static void kvm_arm_timer_write(struct kvm_vcpu *vcpu, { switch (treg) { case TIMER_REG_TVAL: - timer->cnt_cval = kvm_phys_timer_read() - timer->cntvoff + val; + timer->cnt_cval = kvm_phys_timer_read() - timer->cntvoff + (s32)val; break; case TIMER_REG_CTL: