| Message ID | 20191216100111.17122-1-yangbo.lu@nxp.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | clk: qoriq: add ls1088a hwaccel clocks support | expand |
Any comments? Thanks! Best regards, Yangbo Lu > -----Original Message----- > From: Yangbo Lu <yangbo.lu@nxp.com> > Sent: Monday, December 16, 2019 6:01 PM > To: Michael Turquette <mturquette@baylibre.com>; Stephen Boyd > <sboyd@kernel.org>; linux-clk@vger.kernel.org > Cc: Y.b. Lu <yangbo.lu@nxp.com> > Subject: [PATCH] clk: qoriq: add ls1088a hwaccel clocks support > > This patch is to add hwaccel clocks information for ls1088a. > > Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> > --- > drivers/clk/clk-qoriq.c | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c > index bed140f..d5946f7 100644 > --- a/drivers/clk/clk-qoriq.c > +++ b/drivers/clk/clk-qoriq.c > @@ -342,6 +342,32 @@ static const struct clockgen_muxinfo ls1046a_hwa2 > = { > }, > }; > > +static const struct clockgen_muxinfo ls1088a_hwa1 = { > + { > + {}, > + { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, > + { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, > + { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, > + { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, > + {}, > + { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, > + { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, > + }, > +}; > + > +static const struct clockgen_muxinfo ls1088a_hwa2 = { > + { > + {}, > + { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, > + { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, > + { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, > + { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, > + {}, > + { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, > + { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, > + }, > +}; > + > static const struct clockgen_muxinfo ls1012a_cmux = { > { > [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, > @@ -607,6 +633,9 @@ static const struct clockgen_chipinfo chipinfo[] = { > .cmux_groups = { > &clockgen2_cmux_cga12 > }, > + .hwaccel = { > + &ls1088a_hwa1, &ls1088a_hwa2 > + }, > .cmux_to_group = { > 0, 0, -1 > }, > -- > 2.7.4
Hi Stephen, Could you help to review and merge the patch? Thanks :) Best regards, Yangbo Lu > -----Original Message----- > From: Y.b. Lu > Sent: Friday, December 20, 2019 11:58 AM > To: Michael Turquette <mturquette@baylibre.com>; Stephen Boyd > <sboyd@kernel.org>; linux-clk@vger.kernel.org > Subject: RE: [PATCH] clk: qoriq: add ls1088a hwaccel clocks support > > Any comments? > Thanks! > > Best regards, > Yangbo Lu > > > -----Original Message----- > > From: Yangbo Lu <yangbo.lu@nxp.com> > > Sent: Monday, December 16, 2019 6:01 PM > > To: Michael Turquette <mturquette@baylibre.com>; Stephen Boyd > > <sboyd@kernel.org>; linux-clk@vger.kernel.org > > Cc: Y.b. Lu <yangbo.lu@nxp.com> > > Subject: [PATCH] clk: qoriq: add ls1088a hwaccel clocks support > > > > This patch is to add hwaccel clocks information for ls1088a. > > > > Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> > > --- > > drivers/clk/clk-qoriq.c | 29 +++++++++++++++++++++++++++++ > > 1 file changed, 29 insertions(+) > > > > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c > > index bed140f..d5946f7 100644 > > --- a/drivers/clk/clk-qoriq.c > > +++ b/drivers/clk/clk-qoriq.c > > @@ -342,6 +342,32 @@ static const struct clockgen_muxinfo > ls1046a_hwa2 > > = { > > }, > > }; > > > > +static const struct clockgen_muxinfo ls1088a_hwa1 = { > > + { > > + {}, > > + { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, > > + { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, > > + { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, > > + { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, > > + {}, > > + { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, > > + { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, > > + }, > > +}; > > + > > +static const struct clockgen_muxinfo ls1088a_hwa2 = { > > + { > > + {}, > > + { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, > > + { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, > > + { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, > > + { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, > > + {}, > > + { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, > > + { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, > > + }, > > +}; > > + > > static const struct clockgen_muxinfo ls1012a_cmux = { > > { > > [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, > > @@ -607,6 +633,9 @@ static const struct clockgen_chipinfo chipinfo[] = { > > .cmux_groups = { > > &clockgen2_cmux_cga12 > > }, > > + .hwaccel = { > > + &ls1088a_hwa1, &ls1088a_hwa2 > > + }, > > .cmux_to_group = { > > 0, 0, -1 > > }, > > -- > > 2.7.4
Quoting Yangbo Lu (2019-12-16 02:01:11) > This patch is to add hwaccel clocks information for ls1088a. > > Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> > --- Applied to clk-next
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index bed140f..d5946f7 100644 --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c @@ -342,6 +342,32 @@ static const struct clockgen_muxinfo ls1046a_hwa2 = { }, }; +static const struct clockgen_muxinfo ls1088a_hwa1 = { + { + {}, + { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, + { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, + { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, + { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, + {}, + { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, + { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, + }, +}; + +static const struct clockgen_muxinfo ls1088a_hwa2 = { + { + {}, + { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, + { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, + { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, + { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, + {}, + { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, + { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, + }, +}; + static const struct clockgen_muxinfo ls1012a_cmux = { { [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, @@ -607,6 +633,9 @@ static const struct clockgen_chipinfo chipinfo[] = { .cmux_groups = { &clockgen2_cmux_cga12 }, + .hwaccel = { + &ls1088a_hwa1, &ls1088a_hwa2 + }, .cmux_to_group = { 0, 0, -1 },
This patch is to add hwaccel clocks information for ls1088a. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> --- drivers/clk/clk-qoriq.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)