diff mbox series

[v2,kvmtool,18/30] hw/vesa: Set the size for BAR 0

Message ID 20200123134805.1993-19-alexandru.elisei@arm.com (mailing list archive)
State New, archived
Headers show
Series Add reassignable BARs and PCIE 1.1 support | expand

Commit Message

Alexandru Elisei Jan. 23, 2020, 1:47 p.m. UTC
BAR 0 is an I/O BAR and is registered as an ioport region. Let's set its
size, so a guest can actually use it.

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
---
 hw/vesa.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Andre Przywara Feb. 3, 2020, 12:20 p.m. UTC | #1
On Thu, 23 Jan 2020 13:47:53 +0000
Alexandru Elisei <alexandru.elisei@arm.com> wrote:

> BAR 0 is an I/O BAR and is registered as an ioport region. Let's set its
> size, so a guest can actually use it.

Well, the whole I/O bar emulates as RAZ/WI, so I would be curious how the guest would actually use it, but specifying the size is surely a good thing, so:
 
> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>

Reviewed-by: Andre Przywara <andre.przywara>

Cheers,
Andre

> ---
>  hw/vesa.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/hw/vesa.c b/hw/vesa.c
> index a665736a76d7..e988c0425946 100644
> --- a/hw/vesa.c
> +++ b/hw/vesa.c
> @@ -70,6 +70,7 @@ struct framebuffer *vesa__init(struct kvm *kvm)
>  
>  	vesa_base_addr			= (u16)r;
>  	vesa_pci_device.bar[0]		= cpu_to_le32(vesa_base_addr | PCI_BASE_ADDRESS_SPACE_IO);
> +	vesa_pci_device.bar_size[0]	= PCI_IO_SIZE;
>  	r = device__register(&vesa_device);
>  	if (r < 0)
>  		return ERR_PTR(r);
Alexandru Elisei Feb. 3, 2020, 12:27 p.m. UTC | #2
Hi Andre,

On 2/3/20 12:20 PM, Andre Przywara wrote:
> On Thu, 23 Jan 2020 13:47:53 +0000
> Alexandru Elisei <alexandru.elisei@arm.com> wrote:
>
>> BAR 0 is an I/O BAR and is registered as an ioport region. Let's set its
>> size, so a guest can actually use it.
> Well, the whole I/O bar emulates as RAZ/WI, so I would be curious how the guest would actually use it, but specifying the size is surely a good thing, so:

Yeah, you're right, I was thinking about ARM where ioport are MMIO and you need to
map those address. I'll remove the part about the guest being able to actually use
it in the next iteration of the series.. Is it OK if I keep your Reviewed-by?

>  
>> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
> Reviewed-by: Andre Przywara <andre.przywara>
>
> Cheers,
> Andre
>
>> ---
>>  hw/vesa.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/hw/vesa.c b/hw/vesa.c
>> index a665736a76d7..e988c0425946 100644
>> --- a/hw/vesa.c
>> +++ b/hw/vesa.c
>> @@ -70,6 +70,7 @@ struct framebuffer *vesa__init(struct kvm *kvm)
>>  
>>  	vesa_base_addr			= (u16)r;
>>  	vesa_pci_device.bar[0]		= cpu_to_le32(vesa_base_addr | PCI_BASE_ADDRESS_SPACE_IO);
>> +	vesa_pci_device.bar_size[0]	= PCI_IO_SIZE;
>>  	r = device__register(&vesa_device);
>>  	if (r < 0)
>>  		return ERR_PTR(r);
Andre Przywara Feb. 5, 2020, 5 p.m. UTC | #3
On Mon, 3 Feb 2020 12:27:55 +0000
Alexandru Elisei <alexandru.elisei@arm.com> wrote:

> Hi Andre,
> 
> On 2/3/20 12:20 PM, Andre Przywara wrote:
> > On Thu, 23 Jan 2020 13:47:53 +0000
> > Alexandru Elisei <alexandru.elisei@arm.com> wrote:
> >  
> >> BAR 0 is an I/O BAR and is registered as an ioport region. Let's set its
> >> size, so a guest can actually use it.  
> > Well, the whole I/O bar emulates as RAZ/WI, so I would be curious how the guest would actually use it, but specifying the size is surely a good thing, so:  
> 
> Yeah, you're right, I was thinking about ARM where ioport are MMIO and you need to
> map those address. I'll remove the part about the guest being able to actually use
> it in the next iteration of the series.. Is it OK if I keep your Reviewed-by?

Sure, as I mentioned the patch itself is fine.

Thanks,
Andre.

> >    
> >> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>  
> > Reviewed-by: Andre Przywara <andre.przywara>
> >
> > Cheers,
> > Andre
> >  
> >> ---
> >>  hw/vesa.c | 1 +
> >>  1 file changed, 1 insertion(+)
> >>
> >> diff --git a/hw/vesa.c b/hw/vesa.c
> >> index a665736a76d7..e988c0425946 100644
> >> --- a/hw/vesa.c
> >> +++ b/hw/vesa.c
> >> @@ -70,6 +70,7 @@ struct framebuffer *vesa__init(struct kvm *kvm)
> >>  
> >>  	vesa_base_addr			= (u16)r;
> >>  	vesa_pci_device.bar[0]		= cpu_to_le32(vesa_base_addr | PCI_BASE_ADDRESS_SPACE_IO);
> >> +	vesa_pci_device.bar_size[0]	= PCI_IO_SIZE;
> >>  	r = device__register(&vesa_device);
> >>  	if (r < 0)
> >>  		return ERR_PTR(r);
Alexandru Elisei March 6, 2020, 12:40 p.m. UTC | #4
Hi,

On 2/5/20 5:00 PM, Andre Przywara wrote:
> On Mon, 3 Feb 2020 12:27:55 +0000
> Alexandru Elisei <alexandru.elisei@arm.com> wrote:
>
>> Hi Andre,
>>
>> On 2/3/20 12:20 PM, Andre Przywara wrote:
>>> On Thu, 23 Jan 2020 13:47:53 +0000
>>> Alexandru Elisei <alexandru.elisei@arm.com> wrote:
>>>  
>>>> BAR 0 is an I/O BAR and is registered as an ioport region. Let's set its
>>>> size, so a guest can actually use it.  
>>> Well, the whole I/O bar emulates as RAZ/WI, so I would be curious how the guest would actually use it, but specifying the size is surely a good thing, so:  
>> Yeah, you're right, I was thinking about ARM where ioport are MMIO and you need to
>> map those address. I'll remove the part about the guest being able to actually use
>> it in the next iteration of the series.. Is it OK if I keep your Reviewed-by?
> Sure, as I mentioned the patch itself is fine.
>
> Thanks,
> Andre.
>
>>>    
>>>> Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>  
>>> Reviewed-by: Andre Przywara <andre.przywara>

I'm going to go ahead thinking it was a typo and you meant andre.przywara@arm.com
when posting the next iteration of this series. Please let me know if I got it wrong.

Thanks,
Alex
>>>
>>> Cheers,
>>> Andre
>>>  
>>>> ---
>>>>  hw/vesa.c | 1 +
>>>>  1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/hw/vesa.c b/hw/vesa.c
>>>> index a665736a76d7..e988c0425946 100644
>>>> --- a/hw/vesa.c
>>>> +++ b/hw/vesa.c
>>>> @@ -70,6 +70,7 @@ struct framebuffer *vesa__init(struct kvm *kvm)
>>>>  
>>>>  	vesa_base_addr			= (u16)r;
>>>>  	vesa_pci_device.bar[0]		= cpu_to_le32(vesa_base_addr | PCI_BASE_ADDRESS_SPACE_IO);
>>>> +	vesa_pci_device.bar_size[0]	= PCI_IO_SIZE;
>>>>  	r = device__register(&vesa_device);
>>>>  	if (r < 0)
>>>>  		return ERR_PTR(r);
diff mbox series

Patch

diff --git a/hw/vesa.c b/hw/vesa.c
index a665736a76d7..e988c0425946 100644
--- a/hw/vesa.c
+++ b/hw/vesa.c
@@ -70,6 +70,7 @@  struct framebuffer *vesa__init(struct kvm *kvm)
 
 	vesa_base_addr			= (u16)r;
 	vesa_pci_device.bar[0]		= cpu_to_le32(vesa_base_addr | PCI_BASE_ADDRESS_SPACE_IO);
+	vesa_pci_device.bar_size[0]	= PCI_IO_SIZE;
 	r = device__register(&vesa_device);
 	if (r < 0)
 		return ERR_PTR(r);