| Message ID | 20200203072901.31548-2-dirk.behme@de.bosch.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | [1/3] clk: renesas: r8a7795: Add RPC clocks | expand |
Hi Dirk, On Mon, Feb 3, 2020 at 8:29 AM Dirk Behme <dirk.behme@de.bosch.com> wrote: > Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, > as well as the RPC-IF module clock, in the R-Car M3 (R8A7796) CPG/MSSR > driver. > > Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks"). > > Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Thanks for your patch! Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Before I queue this in clk-renesas-for-v5.7: given the fuzz with the RPC driver, has this been tested successfully? Gr{oetje,eeting}s, Geert
Hi Geert, On 06.02.2020 16:47, Geert Uytterhoeven wrote: > Hi Dirk, > > On Mon, Feb 3, 2020 at 8:29 AM Dirk Behme <dirk.behme@de.bosch.com> wrote: >> Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, >> as well as the RPC-IF module clock, in the R-Car M3 (R8A7796) CPG/MSSR >> driver. >> >> Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks"). >> >> Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> > > Thanks for your patch! > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Before I queue this in clk-renesas-for-v5.7: given the fuzz with the RPC > driver, has this been tested successfully? On a custom r8a7796 with 64MB Hyperflash attached I can read and write it via /dev/mtdx. Read data looks ok. Write data is byte swapped, but this is definitely a big-/little-endian driver issue. And not a clock one ;) Best regards Dirk
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index e8420d3ada94..ba8e20d1ad75 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -46,6 +46,7 @@ enum clk_ids { CLK_S3, CLK_SDSRC, CLK_SSPSRC, + CLK_RPCSRC, CLK_RINT, /* Module Clocks */ @@ -72,6 +73,12 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), + + DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A7796_CLK_RPC), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -215,6 +222,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = { DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2), DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4), DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4), + DEF_MOD("rpc-if", 917, R8A7796_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6), DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6), DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the R-Car M3 (R8A7796) CPG/MSSR driver. Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks"). Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> --- Note: Patch done against today's clk-renesas in renesas-drivers.git drivers/clk/renesas/r8a7796-cpg-mssr.c | 8 ++++++++ 1 file changed, 8 insertions(+)