diff mbox series

[7/7] scsi: ufs-qcom: Delay specific time before gate ref clk

Message ID 1581123030-12023-8-git-send-email-cang@codeaurora.org (mailing list archive)
State New, archived
Headers show
Series None | expand

Commit Message

Can Guo Feb. 8, 2020, 12:50 a.m. UTC 
After enter hibern8, as UFS JEDEC ver 3.0 requires, a specific gating wait
time is required before disable the device reference clock. If it is not
specified, use the old delay.

Signed-off-by: Can Guo <cang@codeaurora.org>
Reviewed-by: Asutosh Das <asutoshd@codeaurora.org>
Reviewed-by: Hongwu Su <hongwus@codeaurora.org>

Comments

Avri Altman Feb. 9, 2020, 7:50 a.m. UTC | #1 
> +                               gating_wait += 10;
> +                               usleep_range(gating_wait, gating_wait + 10);
You didn't addressed Bjorn's comment concerning setting larger upper bound.

Thanks,
Avri
Avri Altman Feb. 9, 2020, 7:58 a.m. UTC | #2 
> 
> > +                               gating_wait += 10;
> > +                               usleep_range(gating_wait, gating_wait + 10);
> You didn't addressed Bjorn's comment concerning setting larger upper
> bound.

Sorry - you did.  Please ignore.
diff mbox series

Patch

diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
index 85d7c17..db14a83 100644
--- a/drivers/scsi/ufs/ufs-qcom.c
+++ b/drivers/scsi/ufs/ufs-qcom.c
@@ -845,11 +845,27 @@  static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
 		/*
 		 * If we are here to disable this clock it might be immediately
 		 * after entering into hibern8 in which case we need to make
-		 * sure that device ref_clk is active at least 1us after the
+		 * sure that device ref_clk is active for specific time after
 		 * hibern8 enter.
 		 */
-		if (!enable)
-			udelay(1);
+		if (!enable) {
+			unsigned long gating_wait;
+
+			gating_wait = host->hba->dev_info.clk_gating_wait_us;
+			if (!gating_wait) {
+				udelay(1);
+			} else {
+				/*
+				 * bRefClkGatingWaitTime defines the minimum
+				 * time for which the reference clock is
+				 * required by device during transition from
+				 * HS-MODE to LS-MODE or HIBERN8 state. Give it
+				 * more delay to be on the safe side.
+				 */
+				gating_wait += 10;
+				usleep_range(gating_wait, gating_wait + 10);
+			}
+		}
 
 		writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);