| Message ID | 20200211184542.29585-3-ionela.voinescu@arm.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | arm64: ARMv8.4 Activity Monitors support | expand |
On 11/02/2020 18:45, Ionela Voinescu wrote: > The activity monitors extension is an optional extension introduced > by the ARMv8.4 CPU architecture. In order to access the activity > monitors counters safely, if desired, the kernel should detect the > presence of the extension through the feature register, and mediate > the access. > > Therefore, disable direct accesses to activity monitors counters > from EL0 (userspace) and trap them to EL1 (kernel). > > To be noted that the ARM64_AMU_EXTN kernel config and the disable_amu > kernel parameter do not have an effect on this code. Given that the > amuserenr_el0 resets to an UNKNOWN value, setting the trap of EL0 > accesses to EL1 is always attempted for safety and security > considerations. Therefore firmware should still ensure accesses to > AMU registers are not trapped in EL2/EL3 as this code cannot be > bypassed if the CPU implements the Activity Monitors Unit. > > Signed-off-by: Ionela Voinescu <ionela.voinescu@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Steve Capper <steve.capper@arm.com> > --- Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
On 11/02/2020 18:45, Ionela Voinescu wrote: > The activity monitors extension is an optional extension introduced > by the ARMv8.4 CPU architecture. In order to access the activity > monitors counters safely, if desired, the kernel should detect the > presence of the extension through the feature register, and mediate > the access. > > Therefore, disable direct accesses to activity monitors counters > from EL0 (userspace) and trap them to EL1 (kernel). > > To be noted that the ARM64_AMU_EXTN kernel config and the disable_amu > kernel parameter do not have an effect on this code. Given that the > amuserenr_el0 resets to an UNKNOWN value, setting the trap of EL0 > accesses to EL1 is always attempted for safety and security > considerations. Therefore firmware should still ensure accesses to > AMU registers are not trapped in EL2/EL3 as this code cannot be > bypassed if the CPU implements the Activity Monitors Unit. > > Signed-off-by: Ionela Voinescu <ionela.voinescu@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Steve Capper <steve.capper@arm.com> Reviewed-by: Valentin Schneider <valentin.schneider@arm.com>
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 2cc0dd8bd9f7..2dc6d7b19831 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -443,6 +443,16 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU 9000: .endm +/* + * reset_amuserenr_el0 - reset AMUSERENR_EL0 if AMUv1 present + */ + .macro reset_amuserenr_el0, tmpreg + mrs \tmpreg, id_aa64pfr0_el1 // Check ID_AA64PFR0_EL1 + ubfx \tmpreg, \tmpreg, #ID_AA64PFR0_AMU_SHIFT, #4 + cbz \tmpreg, .Lskip_\@ // Skip if no AMU present + msr_s SYS_AMUSERENR_EL0, xzr // Disable AMU access from EL0 +.Lskip_\@: + .endm /* * copy_page - copy src to dest using temp registers t1-t8 */ diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index a1e0592d1fbc..d8aae1152c08 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -124,6 +124,7 @@ alternative_endif ubfx x11, x11, #1, #1 msr oslar_el1, x11 reset_pmuserenr_el0 x0 // Disable PMU access from EL0 + reset_amuserenr_el0 x0 // Disable AMU access from EL0 alternative_if ARM64_HAS_RAS_EXTN msr_s SYS_DISR_EL1, xzr @@ -415,6 +416,8 @@ ENTRY(__cpu_setup) isb // Unmask debug exceptions now, enable_dbg // since this is per-cpu reset_pmuserenr_el0 x0 // Disable PMU access from EL0 + reset_amuserenr_el0 x0 // Disable AMU access from EL0 + /* * Memory region attributes for LPAE: *
The activity monitors extension is an optional extension introduced by the ARMv8.4 CPU architecture. In order to access the activity monitors counters safely, if desired, the kernel should detect the presence of the extension through the feature register, and mediate the access. Therefore, disable direct accesses to activity monitors counters from EL0 (userspace) and trap them to EL1 (kernel). To be noted that the ARM64_AMU_EXTN kernel config and the disable_amu kernel parameter do not have an effect on this code. Given that the amuserenr_el0 resets to an UNKNOWN value, setting the trap of EL0 accesses to EL1 is always attempted for safety and security considerations. Therefore firmware should still ensure accesses to AMU registers are not trapped in EL2/EL3 as this code cannot be bypassed if the CPU implements the Activity Monitors Unit. Signed-off-by: Ionela Voinescu <ionela.voinescu@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Steve Capper <steve.capper@arm.com> --- arch/arm64/include/asm/assembler.h | 10 ++++++++++ arch/arm64/mm/proc.S | 3 +++ 2 files changed, 13 insertions(+)