[0/2] Add boot interrupt quirk mechanism for Xeon chipsets

Message

Sean V Kelley Feb. 14, 2020, 9:33 p.m. UTC

When IRQ lines on secondary or higher IO-APICs are masked (e.g.,
Real-Time threaded interrupts), many chipsets redirect IRQs on
this line to the legacy PCH and in turn the base IO-APIC in the
system. The unhandled interrupts on the base IO-APIC will be
identified by the Linux kernel as Spurious Interrupts and can
lead to disabled IRQ lines.

Disabling this legacy PCI interrupt routing is chipset-specific and
varies in mechanism between chipset vendors and across generations.
In some cases the mechanism is exposed to BIOS but not all BIOS
vendors choose to pick it up. With the increasing usage of RT as it
marches towards mainline, additional issues have been raised with
more recent Xeon chipsets.

This patchset disables the boot interrupt on these Xeon chipsets where
this is possible with an additional mechanism.  In addition, this
patchset includes documentation covering the background of this quirk.

Sean V Kelley (2):
  pci: Add boot interrupt quirk mechanism for Xeon chipsets
  Documentation:PCI: Add background on Boot Interrupts

 Documentation/PCI/boot-interrupts.rst | 153 ++++++++++++++++++++++++++
 Documentation/PCI/index.rst           |   1 +
 drivers/pci/quirks.c                  |  80 ++++++++++++--
 3 files changed, 227 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/PCI/boot-interrupts.rst

--
2.25.0

Comments

Thomas Gleixner Feb. 15, 2020, 9:24 a.m. UTC | #1

Sean V Kelley <[e-mail]> writes:
> When IRQ lines on secondary or higher IO-APICs are masked (e.g.,
> Real-Time threaded interrupts), many chipsets redirect IRQs on
> this line to the legacy PCH and in turn the base IO-APIC in the
> system. The unhandled interrupts on the base IO-APIC will be
> identified by the Linux kernel as Spurious Interrupts and can
> lead to disabled IRQ lines.
>
> Disabling this legacy PCI interrupt routing is chipset-specific and
> varies in mechanism between chipset vendors and across generations.
> In some cases the mechanism is exposed to BIOS but not all BIOS
> vendors choose to pick it up. With the increasing usage of RT as it
> marches towards mainline, additional issues have been raised with
> more recent Xeon chipsets.
>
> This patchset disables the boot interrupt on these Xeon chipsets where
> this is possible with an additional mechanism.  In addition, this
> patchset includes documentation covering the background of this quirk.

Well done! The documentation is really appreciated!

Reviewed-by: Thomas Gleixner <[e-mail]>

Thomas Gleixner Feb. 15, 2020, 9:26 a.m. UTC | #2

Thomas Gleixner <[e-mail]> writes:

> Sean V Kelley <[e-mail]> writes:
>> When IRQ lines on secondary or higher IO-APICs are masked (e.g.,
>> Real-Time threaded interrupts), many chipsets redirect IRQs on
>> this line to the legacy PCH and in turn the base IO-APIC in the
>> system. The unhandled interrupts on the base IO-APIC will be
>> identified by the Linux kernel as Spurious Interrupts and can
>> lead to disabled IRQ lines.
>>
>> Disabling this legacy PCI interrupt routing is chipset-specific and
>> varies in mechanism between chipset vendors and across generations.
>> In some cases the mechanism is exposed to BIOS but not all BIOS
>> vendors choose to pick it up. With the increasing usage of RT as it
>> marches towards mainline, additional issues have been raised with
>> more recent Xeon chipsets.
>>
>> This patchset disables the boot interrupt on these Xeon chipsets where
>> this is possible with an additional mechanism.  In addition, this
>> patchset includes documentation covering the background of this quirk.
>
> Well done! The documentation is really appreciated!
>
> Reviewed-by: Thomas Gleixner <[e-mail]>

Bjorn, this should go into stable as well IMO.

Thanks,

        tglx