| Message ID | 1581743758-4475-4-git-send-email-Anson.Huang@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add missing UART DCE/DTE pins macro defines | expand |
On Sat, Feb 15, 2020 at 01:15:54PM +0800, Anson Huang wrote: > Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this > is to distinguish the DCE/DTE functions. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- > arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts > index 832b5c5..d84ea69 100644 > --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts > +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts > @@ -484,31 +484,31 @@ > > pinctrl_uart1: uart1grp { > fsl,pins = < > - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 > - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 > + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 > + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 > >; > }; > > pinctrl_uart2: uart2grp { > fsl,pins = < > - MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 > - MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 > + MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 > + MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 > >; > }; > > pinctrl_uart3: uart3grp { > fsl,pins = < > - MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1 > - MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1 > + MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x1b0b1 > + MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x1b0b1 While reviewing this patch I noticed that the user of this pinctrl group has the property uart-has-rtscts which seems wrong. > >; > }; > > pinctrl_uart5: uart5grp { > fsl,pins = < > - MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 > - MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 > - MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1 > - MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1 > + MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 > + MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 > + MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x1b0b1 > + MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x1b0b1 While the property is missing in &uart5. But the patch is fine, so: Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Best regards Uwe
diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index 832b5c5..d84ea69 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -484,31 +484,31 @@ pinctrl_uart1: uart1grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 >; }; pinctrl_uart3: uart3grp { fsl,pins = < - MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1 - MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1 + MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x1b0b1 + MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x1b0b1 >; }; pinctrl_uart5: uart5grp { fsl,pins = < - MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 - MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 - MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1 - MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 + MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x1b0b1 + MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x1b0b1 >; };
Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this is to distinguish the DCE/DTE functions. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)