| Message ID | 20200218131218.10789-1-alexandre.torgue@st.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add GPIO level-sensitive interrupt support | expand |
On 2/18/20 2:12 PM, Alexandre Torgue wrote: > This series adds the possibility to handle gpio interrupts on level. > > GPIO hardware block is directly linked to EXTI block but EXTI handles > external interrupts only on edge. To be able to handle GPIO interrupt on > level a "hack" is done in gpio irq chip: parent interrupt (exti irq chip) > is retriggered following interrupt type and gpio line value. > > In exti irq chip, retrigger ops function is added. btw. this might be unrelated, but is it possible to have e.g. gpioC2 set as trigger-level-low and gpioD2 set as trigger-edge-falling ? It seems 8eb2dfee9fb1 ("pinctrl: stm32: add lock mechanism for irqmux selection") prevents that.
Hi Marek On 2/18/20 5:25 PM, Marek Vasut wrote: > On 2/18/20 2:12 PM, Alexandre Torgue wrote: >> This series adds the possibility to handle gpio interrupts on level. >> >> GPIO hardware block is directly linked to EXTI block but EXTI handles >> external interrupts only on edge. To be able to handle GPIO interrupt on >> level a "hack" is done in gpio irq chip: parent interrupt (exti irq chip) >> is retriggered following interrupt type and gpio line value. >> >> In exti irq chip, retrigger ops function is added. > > btw. this might be unrelated, but is it possible to have e.g. gpioC2 set > as trigger-level-low and gpioD2 set as trigger-edge-falling ? It seems > 8eb2dfee9fb1 ("pinctrl: stm32: add lock mechanism for irqmux selection") > prevents that. > No it's not possible. Each gpio line doesn't have a dedicated Exti line Each Exti line is muxing between gpio banks. Mapping is done as following: EXTI0 = A0 or B0 or C0 .... or Z0 : selected by Mux EXTI1 = A1 or B1 or C1 ....or Z1 : selected by Mux EXTI2 = A2 or B2 or C2 ....or Z2 : selected by Mux ... regards Alexandre
On 2/18/20 7:10 PM, Alexandre Torgue wrote: > Hi Marek Hi, > On 2/18/20 5:25 PM, Marek Vasut wrote: >> On 2/18/20 2:12 PM, Alexandre Torgue wrote: >>> This series adds the possibility to handle gpio interrupts on level. >>> >>> GPIO hardware block is directly linked to EXTI block but EXTI handles >>> external interrupts only on edge. To be able to handle GPIO interrupt on >>> level a "hack" is done in gpio irq chip: parent interrupt (exti irq >>> chip) >>> is retriggered following interrupt type and gpio line value. >>> >>> In exti irq chip, retrigger ops function is added. >> >> btw. this might be unrelated, but is it possible to have e.g. gpioC2 set >> as trigger-level-low and gpioD2 set as trigger-edge-falling ? It seems >> 8eb2dfee9fb1 ("pinctrl: stm32: add lock mechanism for irqmux selection") >> prevents that. >> > > No it's not possible. Each gpio line doesn't have a dedicated Exti line > Each Exti line is muxing between gpio banks. OK, that confirms my assumption. > Mapping is done as following: > > EXTI0 = A0 or B0 or C0 .... or Z0 : selected by Mux > EXTI1 = A1 or B1 or C1 ....or Z1 : selected by Mux > EXTI2 = A2 or B2 or C2 ....or Z2 : selected by Mux > ... Is it at least possible to have IRQs of the same type on the same exti line? E.g. gpioA2 of trigger-edge-falling and gpioB2 trigger-edge-falling ?
On 2/18/20 7:13 PM, Marek Vasut wrote: > On 2/18/20 7:10 PM, Alexandre Torgue wrote: >> Hi Marek > > Hi, > >> On 2/18/20 5:25 PM, Marek Vasut wrote: >>> On 2/18/20 2:12 PM, Alexandre Torgue wrote: >>>> This series adds the possibility to handle gpio interrupts on level. >>>> >>>> GPIO hardware block is directly linked to EXTI block but EXTI handles >>>> external interrupts only on edge. To be able to handle GPIO interrupt on >>>> level a "hack" is done in gpio irq chip: parent interrupt (exti irq >>>> chip) >>>> is retriggered following interrupt type and gpio line value. >>>> >>>> In exti irq chip, retrigger ops function is added. >>> >>> btw. this might be unrelated, but is it possible to have e.g. gpioC2 set >>> as trigger-level-low and gpioD2 set as trigger-edge-falling ? It seems >>> 8eb2dfee9fb1 ("pinctrl: stm32: add lock mechanism for irqmux selection") >>> prevents that. >>> >> >> No it's not possible. Each gpio line doesn't have a dedicated Exti line >> Each Exti line is muxing between gpio banks. > > OK, that confirms my assumption. > >> Mapping is done as following: >> >> EXTI0 = A0 or B0 or C0 .... or Z0 : selected by Mux >> EXTI1 = A1 or B1 or C1 ....or Z1 : selected by Mux >> EXTI2 = A2 or B2 or C2 ....or Z2 : selected by Mux >> ... > > Is it at least possible to have IRQs of the same type on the same exti > line? E.g. gpioA2 of trigger-edge-falling and gpioB2 trigger-edge-falling ? > Sorry I don't catch your point. If you already succeed to get gpioA2, then you will failed to get gpioB2 but looking at function call stack we could get an other issue. Lets take example where you succeed to get gpioa2 as interrupt (using interrupt bindings) and now you try to do the same for gpiob2, you will have (roughly): stm32_gpio_irq_request_resources (for gpiob2) --> succeed stm32_gpio_set_type | |--> stm32_exti_set_type type -> change exti line 2 trigger registers with gpiob2 binding. stm32_gpio_domain_activate --> failed as exti line2 is already used by gpioa2. So as stm32_gpio_set_type is called before checking than exti line is available, type could be changed and behavior of gpioa2 interrupt broken. Solution would be to move the exti line mux check from stm32_gpio_domain_activate to stm32_gpio_irq_request_resources callback. Regards Alex
On 2/19/20 10:20 AM, Alexandre Torgue wrote: Hi, [...] >>>>> This series adds the possibility to handle gpio interrupts on level. >>>>> >>>>> GPIO hardware block is directly linked to EXTI block but EXTI handles >>>>> external interrupts only on edge. To be able to handle GPIO >>>>> interrupt on >>>>> level a "hack" is done in gpio irq chip: parent interrupt (exti irq >>>>> chip) >>>>> is retriggered following interrupt type and gpio line value. >>>>> >>>>> In exti irq chip, retrigger ops function is added. >>>> >>>> btw. this might be unrelated, but is it possible to have e.g. gpioC2 >>>> set >>>> as trigger-level-low and gpioD2 set as trigger-edge-falling ? It seems >>>> 8eb2dfee9fb1 ("pinctrl: stm32: add lock mechanism for irqmux >>>> selection") >>>> prevents that. >>>> >>> >>> No it's not possible. Each gpio line doesn't have a dedicated Exti line >>> Each Exti line is muxing between gpio banks. >> >> OK, that confirms my assumption. >> >>> Mapping is done as following: >>> >>> EXTI0 = A0 or B0 or C0 .... or Z0 : selected by Mux >>> EXTI1 = A1 or B1 or C1 ....or Z1 : selected by Mux >>> EXTI2 = A2 or B2 or C2 ....or Z2 : selected by Mux >>> ... >> >> Is it at least possible to have IRQs of the same type on the same exti >> line? E.g. gpioA2 of trigger-edge-falling and gpioB2 >> trigger-edge-falling ? >> > > Sorry I don't catch your point. If you already succeed to get gpioA2, > then you will failed to get gpioB2 but looking at function call stack we > could get an other issue. Considering the EXTI line limitations, I'd like to know what kind of IRQ input configuration is allowed/valid and what kind of configuration is not valid. > Lets take example where you succeed to get gpioa2 as interrupt (using > interrupt bindings) and now you try to do the same for gpiob2, you will > have (roughly): > > stm32_gpio_irq_request_resources (for gpiob2) --> succeed > > stm32_gpio_set_type > | > |--> stm32_exti_set_type type -> change exti line 2 trigger registers > with gpiob2 binding. > > stm32_gpio_domain_activate --> failed as exti line2 is already used > by gpioa2. > > So as stm32_gpio_set_type is called before checking than exti line is > available, type could be changed and behavior of gpioa2 interrupt broken. > > Solution would be to move the exti line mux check from > stm32_gpio_domain_activate to stm32_gpio_irq_request_resources callback. So the hardware does support using both gpioA2 and gpioB2 as an interrupt source, for different drivers, if they are of the same interrupt type. Except the current implementation does not permit that. If the interrupt types are different, that is not supported by the hardware. Correct ?
Hi Marek On 2/19/20 6:24 PM, Marek Vasut wrote: > On 2/19/20 10:20 AM, Alexandre Torgue wrote: > Hi, > [...] >>>>>> This series adds the possibility to handle gpio interrupts on level. >>>>>> >>>>>> GPIO hardware block is directly linked to EXTI block but EXTI handles >>>>>> external interrupts only on edge. To be able to handle GPIO >>>>>> interrupt on >>>>>> level a "hack" is done in gpio irq chip: parent interrupt (exti irq >>>>>> chip) >>>>>> is retriggered following interrupt type and gpio line value. >>>>>> >>>>>> In exti irq chip, retrigger ops function is added. >>>>> >>>>> btw. this might be unrelated, but is it possible to have e.g. gpioC2 >>>>> set >>>>> as trigger-level-low and gpioD2 set as trigger-edge-falling ? It seems >>>>> 8eb2dfee9fb1 ("pinctrl: stm32: add lock mechanism for irqmux >>>>> selection") >>>>> prevents that. >>>>> >>>> >>>> No it's not possible. Each gpio line doesn't have a dedicated Exti line >>>> Each Exti line is muxing between gpio banks. >>> >>> OK, that confirms my assumption. >>> >>>> Mapping is done as following: >>>> >>>> EXTI0 = A0 or B0 or C0 .... or Z0 : selected by Mux >>>> EXTI1 = A1 or B1 or C1 ....or Z1 : selected by Mux >>>> EXTI2 = A2 or B2 or C2 ....or Z2 : selected by Mux >>>> ... >>> >>> Is it at least possible to have IRQs of the same type on the same exti >>> line? E.g. gpioA2 of trigger-edge-falling and gpioB2 >>> trigger-edge-falling ? >>> >> >> Sorry I don't catch your point. If you already succeed to get gpioA2, >> then you will failed to get gpioB2 but looking at function call stack we >> could get an other issue. > > Considering the EXTI line limitations, I'd like to know what kind of IRQ > input configuration is allowed/valid and what kind of configuration is > not valid. As a mux is used to select which GPIO[A..Z]_X has to be mapped on exti_X line, only one GPIO can be used on the EXTI line. For example, on EXTI2 you could map either gpioa2 or gpiob2 or ....gpioz2 but not gpioa2 and gpiob2 in the same time. > >> Lets take example where you succeed to get gpioa2 as interrupt (using >> interrupt bindings) and now you try to do the same for gpiob2, you will >> have (roughly): >> >> stm32_gpio_irq_request_resources (for gpiob2) --> succeed >> >> stm32_gpio_set_type >> | >> |--> stm32_exti_set_type type -> change exti line 2 trigger registers >> with gpiob2 binding. >> >> stm32_gpio_domain_activate --> failed as exti line2 is already used >> by gpioa2. >> >> So as stm32_gpio_set_type is called before checking than exti line is >> available, type could be changed and behavior of gpioa2 interrupt broken. >> >> Solution would be to move the exti line mux check from >> stm32_gpio_domain_activate to stm32_gpio_irq_request_resources callback. > > So the hardware does support using both gpioA2 and gpioB2 as an > interrupt source, for different drivers, if they are of the same > interrupt type. Except the current implementation does not permit that. > No hardware doesn't allow it for reason explain above. > If the interrupt types are different, that is not supported by the hardware. > > Correct ? >
On 2/20/20 2:09 PM, Alexandre Torgue wrote: > Hi Marek Hi, > On 2/19/20 6:24 PM, Marek Vasut wrote: >> On 2/19/20 10:20 AM, Alexandre Torgue wrote: >> Hi, >> [...] >>>>>>> This series adds the possibility to handle gpio interrupts on level. >>>>>>> >>>>>>> GPIO hardware block is directly linked to EXTI block but EXTI >>>>>>> handles >>>>>>> external interrupts only on edge. To be able to handle GPIO >>>>>>> interrupt on >>>>>>> level a "hack" is done in gpio irq chip: parent interrupt (exti irq >>>>>>> chip) >>>>>>> is retriggered following interrupt type and gpio line value. >>>>>>> >>>>>>> In exti irq chip, retrigger ops function is added. >>>>>> >>>>>> btw. this might be unrelated, but is it possible to have e.g. gpioC2 >>>>>> set >>>>>> as trigger-level-low and gpioD2 set as trigger-edge-falling ? It >>>>>> seems >>>>>> 8eb2dfee9fb1 ("pinctrl: stm32: add lock mechanism for irqmux >>>>>> selection") >>>>>> prevents that. >>>>>> >>>>> >>>>> No it's not possible. Each gpio line doesn't have a dedicated Exti >>>>> line >>>>> Each Exti line is muxing between gpio banks. >>>> >>>> OK, that confirms my assumption. >>>> >>>>> Mapping is done as following: >>>>> >>>>> EXTI0 = A0 or B0 or C0 .... or Z0 : selected by Mux >>>>> EXTI1 = A1 or B1 or C1 ....or Z1 : selected by Mux >>>>> EXTI2 = A2 or B2 or C2 ....or Z2 : selected by Mux >>>>> ... >>>> >>>> Is it at least possible to have IRQs of the same type on the same exti >>>> line? E.g. gpioA2 of trigger-edge-falling and gpioB2 >>>> trigger-edge-falling ? >>>> >>> >>> Sorry I don't catch your point. If you already succeed to get gpioA2, >>> then you will failed to get gpioB2 but looking at function call stack we >>> could get an other issue. >> >> Considering the EXTI line limitations, I'd like to know what kind of IRQ >> input configuration is allowed/valid and what kind of configuration is >> not valid. > > As a mux is used to select which GPIO[A..Z]_X has to be mapped on exti_X > line, only one GPIO can be used on the EXTI line. > > For example, on EXTI2 you could map either gpioa2 or gpiob2 or > ....gpioz2 but not gpioa2 and gpiob2 in the same time. Got it, thank you for the clarification. Maybe that could be something to improve for MP2 :-)