diff mbox series

ARM: dts: dra7xx-clocks: Fixup IPU1 mux clock parent source

Message ID 20200211155103.23973-1-s-anna@ti.com (mailing list archive)
State New, archived
Headers show
Series ARM: dts: dra7xx-clocks: Fixup IPU1 mux clock parent source | expand

Commit Message

Suman Anna Feb. 11, 2020, 3:51 p.m. UTC
The IPU1 functional clock is the output of a mux clock (represented
by ipu1_gfclk_mux previously) and the clock source for this has been
updated to be sourced from dpll_core_h22x2_ck in commit 39879c7d963e
("ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL").
ipu1_gfclk_mux is an obsolete clock now with the clkctrl conversion,
and this clock source parenting is lost during the new clkctrl layout
conversion.

Remove this stale clock and fix up the clock source for this mux
clock using the latest equivalent clkctrl clock. This restores the
previous logic and ensures that the IPU1 continues to run at the
same frequency of IPU2 and independent of the ABE DPLL.

Fixes: b5f8ffbb6fad ("ARM: dts: dra7: convert to use new clkctrl layout")
Signed-off-by: Suman Anna <s-anna@ti.com>
---
Hi Tony,

Patch on top of 5.6-rc1. Appreciate it if you can include it for the 5.6-rc
cycle.

regards
Suman

 arch/arm/boot/dts/dra7xx-clocks.dtsi | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)

Comments

Tony Lindgren Feb. 20, 2020, 5:52 p.m. UTC | #1
* Suman Anna <s-anna@ti.com> [200211 07:52]:
> The IPU1 functional clock is the output of a mux clock (represented
> by ipu1_gfclk_mux previously) and the clock source for this has been
> updated to be sourced from dpll_core_h22x2_ck in commit 39879c7d963e
> ("ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL").
> ipu1_gfclk_mux is an obsolete clock now with the clkctrl conversion,
> and this clock source parenting is lost during the new clkctrl layout
> conversion.
> 
> Remove this stale clock and fix up the clock source for this mux
> clock using the latest equivalent clkctrl clock. This restores the
> previous logic and ensures that the IPU1 continues to run at the
> same frequency of IPU2 and independent of the ABE DPLL.
> 
> Fixes: b5f8ffbb6fad ("ARM: dts: dra7: convert to use new clkctrl layout")
> Signed-off-by: Suman Anna <s-anna@ti.com>
> ---
> Hi Tony,
> 
> Patch on top of 5.6-rc1. Appreciate it if you can include it for the 5.6-rc
> cycle.

OK applying into fixes thanks.

Tony
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 55cef4cac5f1..dc0a93bccbf1 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -796,16 +796,6 @@ 
 		clock-div = <1>;
 	};
 
-	ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
-		ti,bit-shift = <24>;
-		reg = <0x0520>;
-		assigned-clocks = <&ipu1_gfclk_mux>;
-		assigned-clock-parents = <&dpll_core_h22x2_ck>;
-	};
-
 	dummy_ck: dummy_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
@@ -1564,6 +1554,8 @@ 
 			compatible = "ti,clkctrl";
 			reg = <0x20 0x4>;
 			#clock-cells = <2>;
+			assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
+			assigned-clock-parents = <&dpll_core_h22x2_ck>;
 		};
 
 		ipu_clkctrl: ipu-clkctrl@50 {