| Message ID | 20200227062708.21544-2-vadivel.muruganx.ramuthevar@linux.intel.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | spi: cadence-quadspi: Add support for the Cadence QSPI controller | expand |
On Thu, Feb 27, 2020 at 12:27 AM Ramuthevar,Vadivel MuruganX <vadivel.muruganx.ramuthevar@linux.intel.com> wrote: > > From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> > > Add dt-bindings documentation for Cadence-QSPI controller to support > spi based flash memories. You need to run 'make dt_binding_check' because this doesn't pass. > > Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> > --- > .../devicetree/bindings/mtd/cadence-quadspi.txt | 67 ---------- > .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 142 +++++++++++++++++++++ > 2 files changed, 142 insertions(+), 67 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt > create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml > diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml > new file mode 100644 > index 000000000000..3ad2850c412e > --- /dev/null > +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml > @@ -0,0 +1,142 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Cadence QSPI Flash Controller support > + > +maintainers: > + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> > + > +allOf: > + - $ref: "spi-controller.yaml#" > + > +description: | > + Binding Documentation for Cadence QSPI controller,This controller is > + present in the Intel LGM, Altera SoCFPGA and TI SoCs and this driver > + has been tested On Intel's LGM SoC. > + > + - compatible : should be one of the following: > + Generic default - "cdns,qspi-nor". > + For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". > + For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". > + For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor". The schema below says all this, so drop this part. > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - ti,k2g-qspi > + - const: cdns,qspi-nor > + > + - items: > + - enum: > + - ti,am654-ospi > + - const: cdns,qspi-nor > + > + - items: > + - enum: > + - intel,lgm-qspi > + - const: cdns,qspi-nor These 3 items can be 1 entry (combine the enums). > + > + - items: > + - const: cdns,qspi-nor > + > + reg: > + maxItems: 2 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + cdns,fifo-depth: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + 128 or 256 bytes size of the data FIFO in words. Sounds like constraints. Make them a schema. > + > + cdns,fifo-width: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + 4 byte bus width of the data FIFO in bytes. That's not very clear. It should be schema constraints anyways: enum: [ 4, 8, 12, 16, ...??? ] or: multipleOf: 4 minimum: 4 maximum: ? > + > + cdns,trigger-address: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + 32-bit indirect AHB trigger address. > + > + cdns,rclk-en: > + $ref: /schemas/types.yaml#/definitions/uint32 Wrong type if this is a 'flag' aka boolean. > + description: | > + Flag to indicate that QSPI return clock is used to latch the read data > + rather than the QSPI clock. Make sure that QSPI return clock is populated > + on the board before using this property. > + > +# subnode's properties > +patternProperties: > + "^.*@[0-9a-fA-F]+$": > + type: object > + description: > + flash device uses the subnodes below defined properties. > + > + cdns,read-delay: > + description: > + Delay in 4 microseconds, read capture logic, in clock cycles. Huh? Is it in time or clocks? No unit suffix here, so this needs a type ref. That's what 'make dt_binding_check' fails on. > + > + cdns,tshsl-ns: > + description: | > + Delay in 50 nanoseconds, for the length that the master mode chip select > + outputs are de-asserted between transactions. multipleOf: 50 And so on for the rest. > + > + cdns,tsd2d-ns: > + description: | > + Delay in 50 nanoseconds, between one chip select being de-activated > + and the activation of another. > + > + cdns,tchsh-ns: > + description: | > + Delay in 4 nanoseconds, between last bit of current transaction and > + deasserting the device chip select (qspi_n_ss_out). > + > + cdns,tslch-ns: > + description: | > + Delay in 4 nanoseconds, between setting qspi_n_ss_out low and > + first bit transfer. > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - cdns,fifo-depth > + - cdns,fifo-width > + - cdns,trigger-address > + > +examples: > + - | > + qspi: spi@ff705000 { > + compatible = "cdns,qspi-nor"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0xff705000 0x1000>, > + <0xffa00000 0x1000>; > + interrupts = <0 151 4>; > + clocks = <&qspi_clk>; > + cdns,fifo-depth = <128>; > + cdns,fifo-width = <4>; > + cdns,trigger-address = <0x00000000>; > + > + flash0: n25q00@0 { > + compatible = "jedec,spi-nor"; > + reg = <0x0>; > + cdns,read-delay = <4>; > + cdns,tshsl-ns = <50>; > + cdns,tsd2d-ns = <50>; > + cdns,tchsh-ns = <4>; > + cdns,tslch-ns = <4>; > + }; > + }; > + > -- > 2.11.0 >
On Thu, 27 Feb 2020 14:27:07 +0800, "Ramuthevar,Vadivel MuruganX" wrote: > From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> > > Add dt-bindings documentation for Cadence-QSPI controller to support > spi based flash memories. > > Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> > --- > .../devicetree/bindings/mtd/cadence-quadspi.txt | 67 ---------- > .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 142 +++++++++++++++++++++ > 2 files changed, 142 insertions(+), 67 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt > create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml > My bot found errors running 'make dt_binding_check' on your patch: warning: no schema found in file: Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml: ignoring, error in schema: patternProperties: cdns,read-delay Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml: patternProperties:cdns,read-delay: {'description': 'Delay in 4 microseconds, read capture logic, in clock cycles.'} is not valid under any of the given schemas (Possible causes of the failure): /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml: patternProperties:cdns,read-delay: 'not' is a required property Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/spi/cdns,qspi-nor.example.dts' failed make[1]: *** [Documentation/devicetree/bindings/spi/cdns,qspi-nor.example.dts] Error 1 Makefile:1263: recipe for target 'dt_binding_check' failed make: *** [dt_binding_check] Error 2 See https://patchwork.ozlabs.org/patch/1245559 Please check and re-submit.
Hi Rob, Thank you so much for the review comments... On 28/2/2020 1:07 AM, Rob Herring wrote: > On Thu, Feb 27, 2020 at 12:27 AM Ramuthevar,Vadivel MuruganX > <vadivel.muruganx.ramuthevar@linux.intel.com> wrote: >> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> >> >> Add dt-bindings documentation for Cadence-QSPI controller to support >> spi based flash memories. > You need to run 'make dt_binding_check' because this doesn't pass. Sure, run and fix it. >> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> >> --- >> .../devicetree/bindings/mtd/cadence-quadspi.txt | 67 ---------- >> .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 142 +++++++++++++++++++++ >> 2 files changed, 142 insertions(+), 67 deletions(-) >> delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt >> create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml > >> diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml >> new file mode 100644 >> index 000000000000..3ad2850c412e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml >> @@ -0,0 +1,142 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: "http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#" >> +$schema: "http://devicetree.org/meta-schemas/core.yaml#" >> + >> +title: Cadence QSPI Flash Controller support >> + >> +maintainers: >> + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> >> + >> +allOf: >> + - $ref: "spi-controller.yaml#" >> + >> +description: | >> + Binding Documentation for Cadence QSPI controller,This controller is >> + present in the Intel LGM, Altera SoCFPGA and TI SoCs and this driver >> + has been tested On Intel's LGM SoC. >> + >> + - compatible : should be one of the following: >> + Generic default - "cdns,qspi-nor". >> + For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". >> + For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". >> + For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor". > The schema below says all this, so drop this part. > >> + >> +properties: >> + compatible: >> + oneOf: >> + - items: >> + - enum: >> + - ti,k2g-qspi >> + - const: cdns,qspi-nor >> + >> + - items: >> + - enum: >> + - ti,am654-ospi >> + - const: cdns,qspi-nor >> + >> + - items: >> + - enum: >> + - intel,lgm-qspi >> + - const: cdns,qspi-nor > These 3 items can be 1 entry (combine the enums). Noted, will fix it. > >> + >> + - items: >> + - const: cdns,qspi-nor >> + >> + reg: >> + maxItems: 2 >> + >> + interrupts: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 1 >> + >> + cdns,fifo-depth: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: >> + 128 or 256 bytes size of the data FIFO in words. > Sounds like constraints. Make them a schema. Sure, will make as schema. >> + >> + cdns,fifo-width: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: >> + 4 byte bus width of the data FIFO in bytes. > That's not very clear. It should be schema constraints anyways: > > enum: [ 4, 8, 12, 16, ...??? ] > > or: > > multipleOf: 4 > minimum: 4 > maximum: ? Noted, will fix it. >> + >> + cdns,trigger-address: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: >> + 32-bit indirect AHB trigger address. >> + >> + cdns,rclk-en: >> + $ref: /schemas/types.yaml#/definitions/uint32 > Wrong type if this is a 'flag' aka boolean. Yes , you are correct. >> + description: | >> + Flag to indicate that QSPI return clock is used to latch the read data >> + rather than the QSPI clock. Make sure that QSPI return clock is populated >> + on the board before using this property. >> + >> +# subnode's properties >> +patternProperties: >> + "^.*@[0-9a-fA-F]+$": >> + type: object >> + description: >> + flash device uses the subnodes below defined properties. >> + >> + cdns,read-delay: >> + description: >> + Delay in 4 microseconds, read capture logic, in clock cycles. > Huh? Is it in time or clocks? > > No unit suffix here, so this needs a type ref. That's what 'make > dt_binding_check' fails on. it's clock cycles to adjustable delay, read data delay between the Flash Device data outputs and the controller data inputs >> + >> + cdns,tshsl-ns: >> + description: | >> + Delay in 50 nanoseconds, for the length that the master mode chip select >> + outputs are de-asserted between transactions. > multipleOf: 50 > > And so on for the rest. Okay , Noted. Regards Vadivel >> + >> + cdns,tsd2d-ns: >> + description: | >> + Delay in 50 nanoseconds, between one chip select being de-activated >> + and the activation of another. >> + >> + cdns,tchsh-ns: >> + description: | >> + Delay in 4 nanoseconds, between last bit of current transaction and >> + deasserting the device chip select (qspi_n_ss_out). >> + >> + cdns,tslch-ns: >> + description: | >> + Delay in 4 nanoseconds, between setting qspi_n_ss_out low and >> + first bit transfer. >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - clocks >> + - cdns,fifo-depth >> + - cdns,fifo-width >> + - cdns,trigger-address >> + >> +examples: >> + - | >> + qspi: spi@ff705000 { >> + compatible = "cdns,qspi-nor"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + reg = <0xff705000 0x1000>, >> + <0xffa00000 0x1000>; >> + interrupts = <0 151 4>; >> + clocks = <&qspi_clk>; >> + cdns,fifo-depth = <128>; >> + cdns,fifo-width = <4>; >> + cdns,trigger-address = <0x00000000>; >> + >> + flash0: n25q00@0 { >> + compatible = "jedec,spi-nor"; >> + reg = <0x0>; >> + cdns,read-delay = <4>; >> + cdns,tshsl-ns = <50>; >> + cdns,tsd2d-ns = <50>; >> + cdns,tchsh-ns = <4>; >> + cdns,tslch-ns = <4>; >> + }; >> + }; >> + >> -- >> 2.11.0 >>
Hi Rob, On 28/2/2020 1:07 AM, Rob Herring wrote: > On Thu, 27 Feb 2020 14:27:07 +0800, "Ramuthevar,Vadivel MuruganX" wrote: >> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> >> >> Add dt-bindings documentation for Cadence-QSPI controller to support >> spi based flash memories. >> >> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> >> --- >> .../devicetree/bindings/mtd/cadence-quadspi.txt | 67 ---------- >> .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 142 +++++++++++++++++++++ >> 2 files changed, 142 insertions(+), 67 deletions(-) >> delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt >> create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml >> > My bot found errors running 'make dt_binding_check' on your patch: Thanks!, Sorry for the trouble , next time will run and fix it up. Regards Vadivel > > warning: no schema found in file: Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml: ignoring, error in schema: patternProperties: cdns,read-delay > Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml: patternProperties:cdns,read-delay: {'description': 'Delay in 4 microseconds, read capture logic, in clock cycles.'} is not valid under any of the given schemas (Possible causes of the failure): > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml: patternProperties:cdns,read-delay: 'not' is a required property > > Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/spi/cdns,qspi-nor.example.dts' failed > make[1]: *** [Documentation/devicetree/bindings/spi/cdns,qspi-nor.example.dts] Error 1 > Makefile:1263: recipe for target 'dt_binding_check' failed > make: *** [dt_binding_check] Error 2 > > See https://patchwork.ozlabs.org/patch/1245559 > Please check and re-submit.
diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt deleted file mode 100644 index 945be7d5b236..000000000000 --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Cadence Quad SPI controller - -Required properties: -- compatible : should be one of the following: - Generic default - "cdns,qspi-nor". - For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". - For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". -- reg : Contains two entries, each of which is a tuple consisting of a - physical address and length. The first entry is the address and - length of the controller register set. The second entry is the - address and length of the QSPI Controller data area. -- interrupts : Unit interrupt specifier for the controller interrupt. -- clocks : phandle to the Quad SPI clock. -- cdns,fifo-depth : Size of the data FIFO in words. -- cdns,fifo-width : Bus width of the data FIFO in bytes. -- cdns,trigger-address : 32-bit indirect AHB trigger address. - -Optional properties: -- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. -- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch - the read data rather than the QSPI clock. Make sure that QSPI return - clock is populated on the board before using this property. - -Optional subnodes: -Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional -custom properties: -- cdns,read-delay : Delay for read capture logic, in clock cycles -- cdns,tshsl-ns : Delay in nanoseconds for the length that the master - mode chip select outputs are de-asserted between - transactions. -- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being - de-activated and the activation of another. -- cdns,tchsh-ns : Delay in nanoseconds between last bit of current - transaction and deasserting the device chip select - (qspi_n_ss_out). -- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low - and first bit transfer. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include either "qspi" and/or "qspi-ocp". - -Example: - - qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; - interrupts = <0 151 4>; - clocks = <&qspi_clk>; - cdns,is-decoded-cs; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; - reset-names = "qspi", "qspi-ocp"; - - flash0: n25q00@0 { - ... - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml new file mode 100644 index 000000000000..3ad2850c412e --- /dev/null +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence QSPI Flash Controller support + +maintainers: + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> + +allOf: + - $ref: "spi-controller.yaml#" + +description: | + Binding Documentation for Cadence QSPI controller,This controller is + present in the Intel LGM, Altera SoCFPGA and TI SoCs and this driver + has been tested On Intel's LGM SoC. + + - compatible : should be one of the following: + Generic default - "cdns,qspi-nor". + For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". + For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". + For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor". + +properties: + compatible: + oneOf: + - items: + - enum: + - ti,k2g-qspi + - const: cdns,qspi-nor + + - items: + - enum: + - ti,am654-ospi + - const: cdns,qspi-nor + + - items: + - enum: + - intel,lgm-qspi + - const: cdns,qspi-nor + + - items: + - const: cdns,qspi-nor + + reg: + maxItems: 2 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + cdns,fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + 128 or 256 bytes size of the data FIFO in words. + + cdns,fifo-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + 4 byte bus width of the data FIFO in bytes. + + cdns,trigger-address: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + 32-bit indirect AHB trigger address. + + cdns,rclk-en: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Flag to indicate that QSPI return clock is used to latch the read data + rather than the QSPI clock. Make sure that QSPI return clock is populated + on the board before using this property. + +# subnode's properties +patternProperties: + "^.*@[0-9a-fA-F]+$": + type: object + description: + flash device uses the subnodes below defined properties. + + cdns,read-delay: + description: + Delay in 4 microseconds, read capture logic, in clock cycles. + + cdns,tshsl-ns: + description: | + Delay in 50 nanoseconds, for the length that the master mode chip select + outputs are de-asserted between transactions. + + cdns,tsd2d-ns: + description: | + Delay in 50 nanoseconds, between one chip select being de-activated + and the activation of another. + + cdns,tchsh-ns: + description: | + Delay in 4 nanoseconds, between last bit of current transaction and + deasserting the device chip select (qspi_n_ss_out). + + cdns,tslch-ns: + description: | + Delay in 4 nanoseconds, between setting qspi_n_ss_out low and + first bit transfer. + +required: + - compatible + - reg + - interrupts + - clocks + - cdns,fifo-depth + - cdns,fifo-width + - cdns,trigger-address + +examples: + - | + qspi: spi@ff705000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + + flash0: n25q00@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; + }; +