| Message ID | 20200221182503.28317-8-logang@deltatee.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Allow setting caching mode in arch_add_memory() for P2PDMA | expand |
On Fri, Feb 21, 2020 at 10:25 AM Logan Gunthorpe <logang@deltatee.com> wrote: > > PCI BAR IO memory should never be mapped as WB, however prior to this > the PAT bits were set WB and it was typically overridden by MTRR > registers set by the firmware. > > Set PCI P2PDMA memory to be WC (writecombining) as the only current > user (the NVMe CMB) was originally mapped WC before the P2PDMA code > replaced the mapping with devm_memremap_pages(). Will the change to UC regress this existing use case? > > Future use-cases may need to generalize this by adding flags to > select the caching type, as some P2PDMA cases will not want WC. > However, those use-cases are not upstream yet and this can be changed > when they arrive. > > Cc: Dan Williams <dan.j.williams@intel.com> > Cc: Christoph Hellwig <hch@lst.de> > Cc: Jason Gunthorpe <jgg@ziepe.ca> > Signed-off-by: Logan Gunthorpe <logang@deltatee.com> > --- > mm/memremap.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/mm/memremap.c b/mm/memremap.c > index 06742372a203..8d141c3e3364 100644 > --- a/mm/memremap.c > +++ b/mm/memremap.c > @@ -190,7 +190,10 @@ void *memremap_pages(struct dev_pagemap *pgmap, int nid) > } > break; > case MEMORY_DEVICE_DEVDAX: > + need_devmap_managed = false; > + break; > case MEMORY_DEVICE_PCI_P2PDMA: > + params.pgprot = pgprot_writecombine(params.pgprot); Approach looks good to me, modulo Jason's comment that this should be UC. Upcoming DAX changes will want to pass this via pgmap, but as you say this can wait for this changes to arrive. After change to UC: Reviewed-by: Dan Williams <dan.j.williams@intel.com>
On 2020-02-29 3:47 p.m., Dan Williams wrote: > On Fri, Feb 21, 2020 at 10:25 AM Logan Gunthorpe <logang@deltatee.com> wrote: >> >> PCI BAR IO memory should never be mapped as WB, however prior to this >> the PAT bits were set WB and it was typically overridden by MTRR >> registers set by the firmware. >> >> Set PCI P2PDMA memory to be WC (writecombining) as the only current >> user (the NVMe CMB) was originally mapped WC before the P2PDMA code >> replaced the mapping with devm_memremap_pages(). > > Will the change to UC regress this existing use case? I don't think so. They've been essentially mapped UC for a long time now (since the P2PDMA patch set was merged) and nobody has complained.
diff --git a/mm/memremap.c b/mm/memremap.c index 06742372a203..8d141c3e3364 100644 --- a/mm/memremap.c +++ b/mm/memremap.c @@ -190,7 +190,10 @@ void *memremap_pages(struct dev_pagemap *pgmap, int nid) } break; case MEMORY_DEVICE_DEVDAX: + need_devmap_managed = false; + break; case MEMORY_DEVICE_PCI_P2PDMA: + params.pgprot = pgprot_writecombine(params.pgprot); need_devmap_managed = false; break; default:
PCI BAR IO memory should never be mapped as WB, however prior to this the PAT bits were set WB and it was typically overridden by MTRR registers set by the firmware. Set PCI P2PDMA memory to be WC (writecombining) as the only current user (the NVMe CMB) was originally mapped WC before the P2PDMA code replaced the mapping with devm_memremap_pages(). Future use-cases may need to generalize this by adding flags to select the caching type, as some P2PDMA cases will not want WC. However, those use-cases are not upstream yet and this can be changed when they arrive. Cc: Dan Williams <dan.j.williams@intel.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Jason Gunthorpe <jgg@ziepe.ca> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> --- mm/memremap.c | 3 +++ 1 file changed, 3 insertions(+)