| Message ID | 1583173424-21832-2-git-send-email-jcrouse@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | msm/gpu/a6xx: use the DMA-API for GMU memory allocations | expand |
Hi Jordan. On Mon, Mar 02, 2020 at 11:23:43AM -0700, Jordan Crouse wrote: > Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old > text bindings. > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > --- > > .../devicetree/bindings/display/msm/gmu.txt | 116 ------------------- > - > -Required properties: > -- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu" > - for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu" > - Note that you need to list the less specific "qcom,adreno-gmu" > - for generic matches and the more specific identifier to identify > - the specific device. > -- reg: Physical base address and length of the GMU registers. > -- reg-names: Matching names for the register regions > - * "gmu" > - * "gmu_pdc" > - * "gmu_pdc_seg" > -- interrupts: The interrupt signals from the GMU. > -- interrupt-names: Matching names for the interrupts > - * "hfi" > - * "gmu" > -- clocks: phandles to the device clocks > -- clock-names: Matching names for the clocks > - * "gmu" > - * "cxo" > - * "axi" > - * "mnoc" The new binding - and arch/arm64/boot/dts/qcom/sdm845.dtsi agrees that "mnoc" is wrong. > -- power-domains: should be: > - <&clock_gpucc GPU_CX_GDSC> > - <&clock_gpucc GPU_GX_GDSC> > -- power-domain-names: Matching names for the power domains > -- iommus: phandle to the adreno iommu > -- operating-points-v2: phandle to the OPP operating points > - > -Optional properties: > -- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon > - SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml. This property is not included in the new binding. Everything else looked fine to me. With sram added - or expalined in commit why it is dropped: Acked-by: Sam Ravnborg <sam@ravnborg.org> Sam
On Mon, Mar 02, 2020 at 09:49:06PM +0100, Sam Ravnborg wrote: > Hi Jordan. > > On Mon, Mar 02, 2020 at 11:23:43AM -0700, Jordan Crouse wrote: > > Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old > > text bindings. > > > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > > --- > > > > .../devicetree/bindings/display/msm/gmu.txt | 116 ------------------- > > - > > -Required properties: > > -- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu" > > - for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu" > > - Note that you need to list the less specific "qcom,adreno-gmu" > > - for generic matches and the more specific identifier to identify > > - the specific device. > > -- reg: Physical base address and length of the GMU registers. > > -- reg-names: Matching names for the register regions > > - * "gmu" > > - * "gmu_pdc" > > - * "gmu_pdc_seg" > > -- interrupts: The interrupt signals from the GMU. > > -- interrupt-names: Matching names for the interrupts > > - * "hfi" > > - * "gmu" > > -- clocks: phandles to the device clocks > > -- clock-names: Matching names for the clocks > > - * "gmu" > > - * "cxo" > > - * "axi" > > - * "mnoc" > The new binding - and arch/arm64/boot/dts/qcom/sdm845.dtsi agrees that > "mnoc" is wrong. > > > -- power-domains: should be: > > - <&clock_gpucc GPU_CX_GDSC> > > - <&clock_gpucc GPU_GX_GDSC> > > -- power-domain-names: Matching names for the power domains > > -- iommus: phandle to the adreno iommu > > -- operating-points-v2: phandle to the OPP operating points > > - > > -Optional properties: > > -- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon > > - SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml. > This property is not included in the new binding. Yeah, that guy shouldn't be here. I'm not sure how it got there in the first place but I'll update the commit log. Thanks for the poke. Jordan > Everything else looked fine to me. > With sram added - or expalined in commit why it is dropped: > Acked-by: Sam Ravnborg <sam@ravnborg.org> > > Sam > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno
On Tue, Mar 3, 2020 at 8:43 AM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > On Mon, Mar 02, 2020 at 09:49:06PM +0100, Sam Ravnborg wrote: > > Hi Jordan. > > > > On Mon, Mar 02, 2020 at 11:23:43AM -0700, Jordan Crouse wrote: > > > Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old > > > text bindings. > > > > > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > > > --- > > > > > > .../devicetree/bindings/display/msm/gmu.txt | 116 ------------------- > > > - > > > -Required properties: > > > -- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu" > > > - for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu" > > > - Note that you need to list the less specific "qcom,adreno-gmu" > > > - for generic matches and the more specific identifier to identify > > > - the specific device. > > > -- reg: Physical base address and length of the GMU registers. > > > -- reg-names: Matching names for the register regions > > > - * "gmu" > > > - * "gmu_pdc" > > > - * "gmu_pdc_seg" > > > -- interrupts: The interrupt signals from the GMU. > > > -- interrupt-names: Matching names for the interrupts > > > - * "hfi" > > > - * "gmu" > > > -- clocks: phandles to the device clocks > > > -- clock-names: Matching names for the clocks > > > - * "gmu" > > > - * "cxo" > > > - * "axi" > > > - * "mnoc" > > The new binding - and arch/arm64/boot/dts/qcom/sdm845.dtsi agrees that > > "mnoc" is wrong. > > > > > -- power-domains: should be: > > > - <&clock_gpucc GPU_CX_GDSC> > > > - <&clock_gpucc GPU_GX_GDSC> > > > -- power-domain-names: Matching names for the power domains > > > -- iommus: phandle to the adreno iommu > > > -- operating-points-v2: phandle to the OPP operating points > > > - > > > -Optional properties: > > > -- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon > > > - SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml. > > This property is not included in the new binding. > > Yeah, that guy shouldn't be here. I'm not sure how it got there in the first > place but I'll update the commit log. Thanks for the poke. I thought this was something Brian M added for older targets (A4XX?). Perhaps he should chime in? > > Jordan > > > Everything else looked fine to me. > > With sram added - or expalined in commit why it is dropped: > > Acked-by: Sam Ravnborg <sam@ravnborg.org> > > > > Sam > > _______________________________________________ > > Freedreno mailing list > > Freedreno@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/freedreno > > -- > The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno
On Tue, Mar 03, 2020 at 08:50:28AM -0700, Jeffrey Hugo wrote: > On Tue, Mar 3, 2020 at 8:43 AM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > > > On Mon, Mar 02, 2020 at 09:49:06PM +0100, Sam Ravnborg wrote: > > > Hi Jordan. > > > > > > On Mon, Mar 02, 2020 at 11:23:43AM -0700, Jordan Crouse wrote: > > > > Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old > > > > text bindings. > > > > > > > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > > > > --- > > > > > > > > .../devicetree/bindings/display/msm/gmu.txt | 116 ------------------- > > > > - > > > > -Required properties: > > > > -- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu" > > > > - for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu" > > > > - Note that you need to list the less specific "qcom,adreno-gmu" > > > > - for generic matches and the more specific identifier to identify > > > > - the specific device. > > > > -- reg: Physical base address and length of the GMU registers. > > > > -- reg-names: Matching names for the register regions > > > > - * "gmu" > > > > - * "gmu_pdc" > > > > - * "gmu_pdc_seg" > > > > -- interrupts: The interrupt signals from the GMU. > > > > -- interrupt-names: Matching names for the interrupts > > > > - * "hfi" > > > > - * "gmu" > > > > -- clocks: phandles to the device clocks > > > > -- clock-names: Matching names for the clocks > > > > - * "gmu" > > > > - * "cxo" > > > > - * "axi" > > > > - * "mnoc" > > > The new binding - and arch/arm64/boot/dts/qcom/sdm845.dtsi agrees that > > > "mnoc" is wrong. > > > > > > > -- power-domains: should be: > > > > - <&clock_gpucc GPU_CX_GDSC> > > > > - <&clock_gpucc GPU_GX_GDSC> > > > > -- power-domain-names: Matching names for the power domains > > > > -- iommus: phandle to the adreno iommu > > > > -- operating-points-v2: phandle to the OPP operating points > > > > - > > > > -Optional properties: > > > > -- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon > > > > - SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml. > > > This property is not included in the new binding. > > > > Yeah, that guy shouldn't be here. I'm not sure how it got there in the first > > place but I'll update the commit log. Thanks for the poke. > > I thought this was something Brian M added for older targets (A4XX?). > Perhaps he should chime in? Yes, this is needed for older systems with a3xx and a4xx GPUs. Brian
On Tue, Mar 03, 2020 at 10:54:05AM -0500, Brian Masney wrote: > On Tue, Mar 03, 2020 at 08:50:28AM -0700, Jeffrey Hugo wrote: > > On Tue, Mar 3, 2020 at 8:43 AM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > > > > > On Mon, Mar 02, 2020 at 09:49:06PM +0100, Sam Ravnborg wrote: > > > > Hi Jordan. > > > > > > > > On Mon, Mar 02, 2020 at 11:23:43AM -0700, Jordan Crouse wrote: > > > > > Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old > > > > > text bindings. > > > > > > > > > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > > > > > --- > > > > > > > > > > .../devicetree/bindings/display/msm/gmu.txt | 116 ------------------- > > > > > - > > > > > -Required properties: > > > > > -- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu" > > > > > - for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu" > > > > > - Note that you need to list the less specific "qcom,adreno-gmu" > > > > > - for generic matches and the more specific identifier to identify > > > > > - the specific device. > > > > > -- reg: Physical base address and length of the GMU registers. > > > > > -- reg-names: Matching names for the register regions > > > > > - * "gmu" > > > > > - * "gmu_pdc" > > > > > - * "gmu_pdc_seg" > > > > > -- interrupts: The interrupt signals from the GMU. > > > > > -- interrupt-names: Matching names for the interrupts > > > > > - * "hfi" > > > > > - * "gmu" > > > > > -- clocks: phandles to the device clocks > > > > > -- clock-names: Matching names for the clocks > > > > > - * "gmu" > > > > > - * "cxo" > > > > > - * "axi" > > > > > - * "mnoc" > > > > The new binding - and arch/arm64/boot/dts/qcom/sdm845.dtsi agrees that > > > > "mnoc" is wrong. > > > > > > > > > -- power-domains: should be: > > > > > - <&clock_gpucc GPU_CX_GDSC> > > > > > - <&clock_gpucc GPU_GX_GDSC> > > > > > -- power-domain-names: Matching names for the power domains > > > > > -- iommus: phandle to the adreno iommu > > > > > -- operating-points-v2: phandle to the OPP operating points > > > > > - > > > > > -Optional properties: > > > > > -- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon > > > > > - SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml. > > > > This property is not included in the new binding. > > > > > > Yeah, that guy shouldn't be here. I'm not sure how it got there in the first > > > place but I'll update the commit log. Thanks for the poke. > > > > I thought this was something Brian M added for older targets (A4XX?). > > Perhaps he should chime in? > > Yes, this is needed for older systems with a3xx and a4xx GPUs. Okay, this got added to the wrong place. The GMU is a specific entity only valid for a6xx targets. From the looks of the example the sram should be in the GPU definition. Do you want to submit a patch to move it or should I (and lets hope Rob doesn't insist on converting GPU to YAML). Jordan > Brian
On Tue, Mar 03, 2020 at 10:01:59AM -0700, Jordan Crouse wrote: > On Tue, Mar 03, 2020 at 10:54:05AM -0500, Brian Masney wrote: > > On Tue, Mar 03, 2020 at 08:50:28AM -0700, Jeffrey Hugo wrote: > > > On Tue, Mar 3, 2020 at 8:43 AM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > > > > > > > On Mon, Mar 02, 2020 at 09:49:06PM +0100, Sam Ravnborg wrote: > > > > > Hi Jordan. > > > > > > > > > > On Mon, Mar 02, 2020 at 11:23:43AM -0700, Jordan Crouse wrote: > > > > > > Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old > > > > > > text bindings. > > > > > > > > > > > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > > > > > > --- > > > > > > > > > > > > .../devicetree/bindings/display/msm/gmu.txt | 116 ------------------- > > > > > > - > > > > > > -Required properties: > > > > > > -- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu" > > > > > > - for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu" > > > > > > - Note that you need to list the less specific "qcom,adreno-gmu" > > > > > > - for generic matches and the more specific identifier to identify > > > > > > - the specific device. > > > > > > -- reg: Physical base address and length of the GMU registers. > > > > > > -- reg-names: Matching names for the register regions > > > > > > - * "gmu" > > > > > > - * "gmu_pdc" > > > > > > - * "gmu_pdc_seg" > > > > > > -- interrupts: The interrupt signals from the GMU. > > > > > > -- interrupt-names: Matching names for the interrupts > > > > > > - * "hfi" > > > > > > - * "gmu" > > > > > > -- clocks: phandles to the device clocks > > > > > > -- clock-names: Matching names for the clocks > > > > > > - * "gmu" > > > > > > - * "cxo" > > > > > > - * "axi" > > > > > > - * "mnoc" > > > > > The new binding - and arch/arm64/boot/dts/qcom/sdm845.dtsi agrees that > > > > > "mnoc" is wrong. > > > > > > > > > > > -- power-domains: should be: > > > > > > - <&clock_gpucc GPU_CX_GDSC> > > > > > > - <&clock_gpucc GPU_GX_GDSC> > > > > > > -- power-domain-names: Matching names for the power domains > > > > > > -- iommus: phandle to the adreno iommu > > > > > > -- operating-points-v2: phandle to the OPP operating points > > > > > > - > > > > > > -Optional properties: > > > > > > -- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon > > > > > > - SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml. > > > > > This property is not included in the new binding. > > > > > > > > Yeah, that guy shouldn't be here. I'm not sure how it got there in the first > > > > place but I'll update the commit log. Thanks for the poke. > > > > > > I thought this was something Brian M added for older targets (A4XX?). > > > Perhaps he should chime in? > > > > Yes, this is needed for older systems with a3xx and a4xx GPUs. > > Okay, this got added to the wrong place. The GMU is a specific entity only > valid for a6xx targets. From the looks of the example the sram should be in the > GPU definition. Do you want to submit a patch to move it or should I (and lets > hope Rob doesn't insist on converting GPU to YAML). I can take care of cleaning this up. I'll do that in a few days. Brian
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt deleted file mode 100644 index bf9c7a2..0000000 --- a/Documentation/devicetree/bindings/display/msm/gmu.txt +++ /dev/null @@ -1,116 +0,0 @@ -Qualcomm adreno/snapdragon GMU (Graphics management unit) - -The GMU is a programmable power controller for the GPU. the CPU controls the -GMU which in turn handles power controls for the GPU. - -Required properties: -- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu" - for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu" - Note that you need to list the less specific "qcom,adreno-gmu" - for generic matches and the more specific identifier to identify - the specific device. -- reg: Physical base address and length of the GMU registers. -- reg-names: Matching names for the register regions - * "gmu" - * "gmu_pdc" - * "gmu_pdc_seg" -- interrupts: The interrupt signals from the GMU. -- interrupt-names: Matching names for the interrupts - * "hfi" - * "gmu" -- clocks: phandles to the device clocks -- clock-names: Matching names for the clocks - * "gmu" - * "cxo" - * "axi" - * "mnoc" -- power-domains: should be: - <&clock_gpucc GPU_CX_GDSC> - <&clock_gpucc GPU_GX_GDSC> -- power-domain-names: Matching names for the power domains -- iommus: phandle to the adreno iommu -- operating-points-v2: phandle to the OPP operating points - -Optional properties: -- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon - SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml. - -Example: - -/ { - ... - - gmu: gmu@506a000 { - compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; - - reg = <0x506a000 0x30000>, - <0xb280000 0x10000>, - <0xb480000 0x10000>; - reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; - - interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hfi", "gmu"; - - clocks = <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - clock-names = "gmu", "cxo", "axi", "memnoc"; - - power-domains = <&gpucc GPU_CX_GDSC>, - <&gpucc GPU_GX_GDSC>; - power-domain-names = "cx", "gx"; - - iommus = <&adreno_smmu 5>; - - operating-points-v2 = <&gmu_opp_table>; - }; -}; - -a3xx example with OCMEM support: - -/ { - ... - - gpu: adreno@fdb00000 { - compatible = "qcom,adreno-330.2", - "qcom,adreno"; - reg = <0xfdb00000 0x10000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "kgsl_3d0_irq"; - clock-names = "core", - "iface", - "mem_iface"; - clocks = <&mmcc OXILI_GFX3D_CLK>, - <&mmcc OXILICX_AHB_CLK>, - <&mmcc OXILICX_AXI_CLK>; - sram = <&gmu_sram>; - power-domains = <&mmcc OXILICX_GDSC>; - operating-points-v2 = <&gpu_opp_table>; - iommus = <&gpu_iommu 0>; - }; - - ocmem@fdd00000 { - compatible = "qcom,msm8974-ocmem"; - - reg = <0xfdd00000 0x2000>, - <0xfec00000 0x180000>; - reg-names = "ctrl", - "mem"; - - clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, - <&mmcc OCMEMCX_OCMEMNOC_CLK>; - clock-names = "core", - "iface"; - - #address-cells = <1>; - #size-cells = <1>; - - gmu_sram: gmu-sram@0 { - reg = <0x0 0x100000>; - ranges = <0 0 0xfec00000 0x100000>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml new file mode 100644 index 0000000..0b8736a --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright 2019-2020, The Linux Foundation, All Rights Reserved +%YAML 1.2 +--- + +$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Devicetree bindings for the GMU attached to certain Adreno GPUs + +maintainers: + - Rob Clark <robdclark@gmail.com> + +description: | + These bindings describe the Graphics Management Unit (GMU) that is attached + to members of the Adreno A6xx GPU family. The GMU provides on-device power + management and support to improve power efficiency and reduce the load on + the CPU. + +properties: + compatible: + items: + - enum: + - qcom,adreno-gmu-630.2 + - const: qcom,adreno-gmu + + reg: + items: + - description: Core GMU registers + - description: GMU PDC registers + - description: GMU PDC sequence registers + + reg-names: + items: + - const: gmu + - const: gmu_pdc + - const: gmu_pdc_seq + + clocks: + items: + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + + clock-names: + items: + - const: gmu + - const: cxo + - const: axi + - const: memnoc + + interrupts: + items: + - description: GMU HFI interrupt + - description: GMU interrupt + + + interrupt-names: + items: + - const: hfi + - const: gmu + + power-domains: + items: + - description: CX power domain + - description: GX power domain + + power-domain-names: + items: + - const: cx + - const: gx + + iommus: + maxItems: 1 + + operating-points-v2: true + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - power-domains + - power-domain-names + - iommus + - operating-points-v2 + +examples: + - | + #include <dt-bindings/clock/qcom,gpucc-sdm845.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, + <0xb280000 0x10000>, + <0xb480000 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + + iommus = <&adreno_smmu 5>; + operating-points-v2 = <&gmu_opp_table>; + };
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old text bindings. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> --- .../devicetree/bindings/display/msm/gmu.txt | 116 ------------------- .../devicetree/bindings/display/msm/gmu.yaml | 123 +++++++++++++++++++++ 2 files changed, 123 insertions(+), 116 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.yaml