| Message ID | 20200316142613.121089-4-npiggin@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | FWNMI fixes / changes | expand |
On Tue, 17 Mar 2020 00:26:08 +1000 Nicholas Piggin <npiggin@gmail.com> wrote: > The FWNMI option must deliver system reset interrupts to their > registered address, and there are a few constraints on the handler > addresses specified in PAPR. Add the system reset address state and > checks. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- Reviewed-by: Greg Kurz <groug@kaod.org> > hw/ppc/spapr.c | 2 ++ > hw/ppc/spapr_rtas.c | 14 +++++++++++++- > include/hw/ppc/spapr.h | 3 ++- > 3 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index b03b26370d..5f93c49706 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -1704,6 +1704,7 @@ static void spapr_machine_reset(MachineState *machine) > > spapr->cas_reboot = false; > > + spapr->fwnmi_system_reset_addr = -1; > spapr->fwnmi_machine_check_addr = -1; > spapr->fwnmi_machine_check_interlock = -1; > > @@ -2023,6 +2024,7 @@ static const VMStateDescription vmstate_spapr_fwnmi = { > .needed = spapr_fwnmi_needed, > .pre_save = spapr_fwnmi_pre_save, > .fields = (VMStateField[]) { > + VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), > VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), > VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), > VMSTATE_END_OF_LIST() > diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c > index 0b8c481593..521e6b0b72 100644 > --- a/hw/ppc/spapr_rtas.c > +++ b/hw/ppc/spapr_rtas.c > @@ -414,6 +414,7 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, > uint32_t nret, target_ulong rets) > { > hwaddr rtas_addr; > + target_ulong sreset_addr, mce_addr; > > if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_OFF) { > rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); > @@ -426,7 +427,18 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, > return; > } > > - spapr->fwnmi_machine_check_addr = rtas_ld(args, 1); > + sreset_addr = rtas_ld(args, 0); > + mce_addr = rtas_ld(args, 1); > + > + /* PAPR requires these are in the first 32M of memory and within RMA */ > + if (sreset_addr >= 32 * MiB || sreset_addr >= spapr->rma_size || > + mce_addr >= 32 * MiB || mce_addr >= spapr->rma_size) { > + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > + return; > + } > + > + spapr->fwnmi_system_reset_addr = sreset_addr; > + spapr->fwnmi_machine_check_addr = mce_addr; > > rtas_st(rets, 0, RTAS_OUT_SUCCESS); > } > diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h > index 64b83402cb..42d64a0368 100644 > --- a/include/hw/ppc/spapr.h > +++ b/include/hw/ppc/spapr.h > @@ -194,9 +194,10 @@ struct SpaprMachineState { > > /* State related to FWNMI option */ > > - /* Machine Check Notification Routine address > + /* System Reset and Machine Check Notification Routine addresses > * registered by "ibm,nmi-register" RTAS call. > */ > + target_ulong fwnmi_system_reset_addr; > target_ulong fwnmi_machine_check_addr; > > /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is
On 2020-03-17 00:26:08 Tue, Nicholas Piggin wrote: > The FWNMI option must deliver system reset interrupts to their > registered address, and there are a few constraints on the handler > addresses specified in PAPR. Add the system reset address state and > checks. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Looks good to me. Reviwed-by: Mahesh Salgaonkar <mahesh@linux.ibm.com> Thanks, -Mahesh. > --- > hw/ppc/spapr.c | 2 ++ > hw/ppc/spapr_rtas.c | 14 +++++++++++++- > include/hw/ppc/spapr.h | 3 ++- > 3 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index b03b26370d..5f93c49706 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -1704,6 +1704,7 @@ static void spapr_machine_reset(MachineState *machine) > > spapr->cas_reboot = false; > > + spapr->fwnmi_system_reset_addr = -1; > spapr->fwnmi_machine_check_addr = -1; > spapr->fwnmi_machine_check_interlock = -1; > > @@ -2023,6 +2024,7 @@ static const VMStateDescription vmstate_spapr_fwnmi = { > .needed = spapr_fwnmi_needed, > .pre_save = spapr_fwnmi_pre_save, > .fields = (VMStateField[]) { > + VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), > VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), > VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), > VMSTATE_END_OF_LIST() > diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c > index 0b8c481593..521e6b0b72 100644 > --- a/hw/ppc/spapr_rtas.c > +++ b/hw/ppc/spapr_rtas.c > @@ -414,6 +414,7 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, > uint32_t nret, target_ulong rets) > { > hwaddr rtas_addr; > + target_ulong sreset_addr, mce_addr; > > if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_OFF) { > rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); > @@ -426,7 +427,18 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, > return; > } > > - spapr->fwnmi_machine_check_addr = rtas_ld(args, 1); > + sreset_addr = rtas_ld(args, 0); > + mce_addr = rtas_ld(args, 1); > + > + /* PAPR requires these are in the first 32M of memory and within RMA */ > + if (sreset_addr >= 32 * MiB || sreset_addr >= spapr->rma_size || > + mce_addr >= 32 * MiB || mce_addr >= spapr->rma_size) { > + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > + return; > + } > + > + spapr->fwnmi_system_reset_addr = sreset_addr; > + spapr->fwnmi_machine_check_addr = mce_addr; > > rtas_st(rets, 0, RTAS_OUT_SUCCESS); > } > diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h > index 64b83402cb..42d64a0368 100644 > --- a/include/hw/ppc/spapr.h > +++ b/include/hw/ppc/spapr.h > @@ -194,9 +194,10 @@ struct SpaprMachineState { > > /* State related to FWNMI option */ > > - /* Machine Check Notification Routine address > + /* System Reset and Machine Check Notification Routine addresses > * registered by "ibm,nmi-register" RTAS call. > */ > + target_ulong fwnmi_system_reset_addr; > target_ulong fwnmi_machine_check_addr; > > /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is > -- > 2.23.0 > >
On 3/16/20 3:26 PM, Nicholas Piggin wrote: > The FWNMI option must deliver system reset interrupts to their > registered address, and there are a few constraints on the handler > addresses specified in PAPR. Add the system reset address state and > checks. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> This is in sync with the latest PAPR 2.9 Reviewed-by: Cédric Le Goater <clg@kaod.org> > --- > hw/ppc/spapr.c | 2 ++ > hw/ppc/spapr_rtas.c | 14 +++++++++++++- > include/hw/ppc/spapr.h | 3 ++- > 3 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index b03b26370d..5f93c49706 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -1704,6 +1704,7 @@ static void spapr_machine_reset(MachineState *machine) > > spapr->cas_reboot = false; > > + spapr->fwnmi_system_reset_addr = -1; > spapr->fwnmi_machine_check_addr = -1; > spapr->fwnmi_machine_check_interlock = -1; > > @@ -2023,6 +2024,7 @@ static const VMStateDescription vmstate_spapr_fwnmi = { > .needed = spapr_fwnmi_needed, > .pre_save = spapr_fwnmi_pre_save, > .fields = (VMStateField[]) { > + VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), > VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), > VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), > VMSTATE_END_OF_LIST() > diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c > index 0b8c481593..521e6b0b72 100644 > --- a/hw/ppc/spapr_rtas.c > +++ b/hw/ppc/spapr_rtas.c > @@ -414,6 +414,7 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, > uint32_t nret, target_ulong rets) > { > hwaddr rtas_addr; > + target_ulong sreset_addr, mce_addr; > > if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_OFF) { > rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); > @@ -426,7 +427,18 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, > return; > } > > - spapr->fwnmi_machine_check_addr = rtas_ld(args, 1); > + sreset_addr = rtas_ld(args, 0); > + mce_addr = rtas_ld(args, 1); > + > + /* PAPR requires these are in the first 32M of memory and within RMA */ > + if (sreset_addr >= 32 * MiB || sreset_addr >= spapr->rma_size || > + mce_addr >= 32 * MiB || mce_addr >= spapr->rma_size) { > + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > + return; > + } > + > + spapr->fwnmi_system_reset_addr = sreset_addr; > + spapr->fwnmi_machine_check_addr = mce_addr; > > rtas_st(rets, 0, RTAS_OUT_SUCCESS); > } > diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h > index 64b83402cb..42d64a0368 100644 > --- a/include/hw/ppc/spapr.h > +++ b/include/hw/ppc/spapr.h > @@ -194,9 +194,10 @@ struct SpaprMachineState { > > /* State related to FWNMI option */ > > - /* Machine Check Notification Routine address > + /* System Reset and Machine Check Notification Routine addresses > * registered by "ibm,nmi-register" RTAS call. > */ > + target_ulong fwnmi_system_reset_addr; > target_ulong fwnmi_machine_check_addr; > > /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is >
On Tue, Mar 17, 2020 at 12:26:08AM +1000, Nicholas Piggin wrote: > The FWNMI option must deliver system reset interrupts to their > registered address, and there are a few constraints on the handler > addresses specified in PAPR. Add the system reset address state and > checks. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Applied to ppc-for-5.0, thanks. > --- > hw/ppc/spapr.c | 2 ++ > hw/ppc/spapr_rtas.c | 14 +++++++++++++- > include/hw/ppc/spapr.h | 3 ++- > 3 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index b03b26370d..5f93c49706 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -1704,6 +1704,7 @@ static void spapr_machine_reset(MachineState *machine) > > spapr->cas_reboot = false; > > + spapr->fwnmi_system_reset_addr = -1; > spapr->fwnmi_machine_check_addr = -1; > spapr->fwnmi_machine_check_interlock = -1; > > @@ -2023,6 +2024,7 @@ static const VMStateDescription vmstate_spapr_fwnmi = { > .needed = spapr_fwnmi_needed, > .pre_save = spapr_fwnmi_pre_save, > .fields = (VMStateField[]) { > + VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), > VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), > VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), > VMSTATE_END_OF_LIST() > diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c > index 0b8c481593..521e6b0b72 100644 > --- a/hw/ppc/spapr_rtas.c > +++ b/hw/ppc/spapr_rtas.c > @@ -414,6 +414,7 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, > uint32_t nret, target_ulong rets) > { > hwaddr rtas_addr; > + target_ulong sreset_addr, mce_addr; > > if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_OFF) { > rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); > @@ -426,7 +427,18 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, > return; > } > > - spapr->fwnmi_machine_check_addr = rtas_ld(args, 1); > + sreset_addr = rtas_ld(args, 0); > + mce_addr = rtas_ld(args, 1); > + > + /* PAPR requires these are in the first 32M of memory and within RMA */ > + if (sreset_addr >= 32 * MiB || sreset_addr >= spapr->rma_size || > + mce_addr >= 32 * MiB || mce_addr >= spapr->rma_size) { > + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > + return; > + } > + > + spapr->fwnmi_system_reset_addr = sreset_addr; > + spapr->fwnmi_machine_check_addr = mce_addr; > > rtas_st(rets, 0, RTAS_OUT_SUCCESS); > } > diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h > index 64b83402cb..42d64a0368 100644 > --- a/include/hw/ppc/spapr.h > +++ b/include/hw/ppc/spapr.h > @@ -194,9 +194,10 @@ struct SpaprMachineState { > > /* State related to FWNMI option */ > > - /* Machine Check Notification Routine address > + /* System Reset and Machine Check Notification Routine addresses > * registered by "ibm,nmi-register" RTAS call. > */ > + target_ulong fwnmi_system_reset_addr; > target_ulong fwnmi_machine_check_addr; > > /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index b03b26370d..5f93c49706 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1704,6 +1704,7 @@ static void spapr_machine_reset(MachineState *machine) spapr->cas_reboot = false; + spapr->fwnmi_system_reset_addr = -1; spapr->fwnmi_machine_check_addr = -1; spapr->fwnmi_machine_check_interlock = -1; @@ -2023,6 +2024,7 @@ static const VMStateDescription vmstate_spapr_fwnmi = { .needed = spapr_fwnmi_needed, .pre_save = spapr_fwnmi_pre_save, .fields = (VMStateField[]) { + VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), VMSTATE_END_OF_LIST() diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 0b8c481593..521e6b0b72 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -414,6 +414,7 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, uint32_t nret, target_ulong rets) { hwaddr rtas_addr; + target_ulong sreset_addr, mce_addr; if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_OFF) { rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); @@ -426,7 +427,18 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, return; } - spapr->fwnmi_machine_check_addr = rtas_ld(args, 1); + sreset_addr = rtas_ld(args, 0); + mce_addr = rtas_ld(args, 1); + + /* PAPR requires these are in the first 32M of memory and within RMA */ + if (sreset_addr >= 32 * MiB || sreset_addr >= spapr->rma_size || + mce_addr >= 32 * MiB || mce_addr >= spapr->rma_size) { + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); + return; + } + + spapr->fwnmi_system_reset_addr = sreset_addr; + spapr->fwnmi_machine_check_addr = mce_addr; rtas_st(rets, 0, RTAS_OUT_SUCCESS); } diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 64b83402cb..42d64a0368 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -194,9 +194,10 @@ struct SpaprMachineState { /* State related to FWNMI option */ - /* Machine Check Notification Routine address + /* System Reset and Machine Check Notification Routine addresses * registered by "ibm,nmi-register" RTAS call. */ + target_ulong fwnmi_system_reset_addr; target_ulong fwnmi_machine_check_addr; /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is
The FWNMI option must deliver system reset interrupts to their registered address, and there are a few constraints on the handler addresses specified in PAPR. Add the system reset address state and checks. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- hw/ppc/spapr.c | 2 ++ hw/ppc/spapr_rtas.c | 14 +++++++++++++- include/hw/ppc/spapr.h | 3 ++- 3 files changed, 17 insertions(+), 2 deletions(-)