| Message ID | 20200318063517.3844-1-manasi.d.navare@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD | expand |
On Tue, 17 Mar 2020, Manasi Navare <manasi.d.navare@intel.com> wrote: > DP sink device sets the Ignore MSA bit in its > DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to > ignore the MSA video timing paramaters and its ability to support > seamless video timing change over a range of timing exposed by > DisplayID and EDID. > This is required for the sink to indicate that it is Adaptive sync > capable. > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Harry Wentland <harry.wentland@amd.com> > Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > include/drm/drm_dp_helper.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index c6119e4c169a..ccd6e2e988b9 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1315,6 +1315,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > DP_ALTERNATE_SCRAMBLER_RESET_CAP; > } > > +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ > +static inline bool > +drm_dp_sink_is_capable_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) From the department of nitpicks, if you read the name of the function aloud, what does it actually mean? Is sink capable of *what*? BR, Jani. > +{ > + return dpcd[DP_DOWN_STREAM_PORT_COUNT] & > + DP_MSA_TIMING_PAR_IGNORED; > +} > + > /* > * DisplayPort AUX channel > */
On Thu, Mar 19, 2020 at 11:59:38AM +0200, Jani Nikula wrote: > On Tue, 17 Mar 2020, Manasi Navare <manasi.d.navare@intel.com> wrote: > > DP sink device sets the Ignore MSA bit in its > > DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to > > ignore the MSA video timing paramaters and its ability to support > > seamless video timing change over a range of timing exposed by > > DisplayID and EDID. > > This is required for the sink to indicate that it is Adaptive sync > > capable. > > > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Cc: Harry Wentland <harry.wentland@amd.com> > > Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > --- > > include/drm/drm_dp_helper.h | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > > index c6119e4c169a..ccd6e2e988b9 100644 > > --- a/include/drm/drm_dp_helper.h > > +++ b/include/drm/drm_dp_helper.h > > @@ -1315,6 +1315,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > > DP_ALTERNATE_SCRAMBLER_RESET_CAP; > > } > > > > +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ > > +static inline bool > > +drm_dp_sink_is_capable_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > > From the department of nitpicks, if you read the name of the function > aloud, what does it actually mean? > > Is sink capable of *what*? As per the DP 1.4 spec, it says this indicates sink's ability to ignore MSA video timing parameters to support seamless video timing change over range of timing exposed in DisplayID and legacy EDID. This query should occur before enabling dynamic video timing change of incoming video stream without valid MSA video timing params. May be i rename it as: drm_dp_sink_capable_video_without_timing_msa() ? Manasi > > BR, > Jani. > > > > +{ > > + return dpcd[DP_DOWN_STREAM_PORT_COUNT] & > > + DP_MSA_TIMING_PAR_IGNORED; > > +} > > + > > /* > > * DisplayPort AUX channel > > */ > > -- > Jani Nikula, Intel Open Source Graphics Center
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index c6119e4c169a..ccd6e2e988b9 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1315,6 +1315,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) DP_ALTERNATE_SCRAMBLER_RESET_CAP; } +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ +static inline bool +drm_dp_sink_is_capable_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DOWN_STREAM_PORT_COUNT] & + DP_MSA_TIMING_PAR_IGNORED; +} + /* * DisplayPort AUX channel */
DP sink device sets the Ignore MSA bit in its DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to ignore the MSA video timing paramaters and its ability to support seamless video timing change over a range of timing exposed by DisplayID and EDID. This is required for the sink to indicate that it is Adaptive sync capable. Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- include/drm/drm_dp_helper.h | 8 ++++++++ 1 file changed, 8 insertions(+)