| Message ID | 20200316095605.12318-1-xiaoyao.li@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] target/i386: Add ARCH_CAPABILITIES related bits into Icelake-Server CPU model | expand |
Hi Xiaoyao,
May be you can add .note for this new version.
for example:
+ .version = 3,
+ .note = "ARCH_CAPABILITIES",
+ .props = (PropValue[]) {
On 3/16/2020 5:56 PM, Xiaoyao Li wrote:
> Current Icelake-Server CPU model lacks all the features enumerated by
> MSR_IA32_ARCH_CAPABILITIES.
>
> Add them, so that guest of "Icelake-Server" can see all of them.
>
> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
> ---
> v2:
> - Add it as a new version.
> ---
> target/i386/cpu.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 92fafa265914..5fba6a2ad6b3 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3496,6 +3496,19 @@ static X86CPUDefinition builtin_x86_defs[] = {
> { /* end of list */ }
> },
> },
> + {
> + .version = 3,
> + .props = (PropValue[]) {
> + { "arch-capabilities", "on" },
> + { "rdctl-no", "on" },
> + { "ibrs-all", "on" },
> + { "skip-l1dfl-vmentry", "on" },
> + { "mds-no", "on" },
> + { "pschange-mc-no", "on" },
> + { "taa-no", "on" },
> + { /* end of list */ }
> + },
> + },
> { /* end of list */ }
> }
> },
> --
> 2.20.1
>
>
On 3/23/2020 10:32 AM, Tao Xu wrote: > Hi Xiaoyao, > > May be you can add .note for this new version. > > for example: > > + .version = 3, > + .note = "ARCH_CAPABILITIES", > + .props = (PropValue[]) { Hi Paolo and Eduardo, Need I spin a new version to add the .note ? Maybe you can add it when queue? Thanks, -Xiaoyao > On 3/16/2020 5:56 PM, Xiaoyao Li wrote: >> Current Icelake-Server CPU model lacks all the features enumerated by >> MSR_IA32_ARCH_CAPABILITIES. >> >> Add them, so that guest of "Icelake-Server" can see all of them. >> >> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> >> --- >> v2: >> - Add it as a new version. >> --- >> target/i386/cpu.c | 13 +++++++++++++ >> 1 file changed, 13 insertions(+) >> >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c >> index 92fafa265914..5fba6a2ad6b3 100644 >> --- a/target/i386/cpu.c >> +++ b/target/i386/cpu.c >> @@ -3496,6 +3496,19 @@ static X86CPUDefinition builtin_x86_defs[] = { >> { /* end of list */ } >> }, >> }, >> + { >> + .version = 3, >> + .props = (PropValue[]) { >> + { "arch-capabilities", "on" }, >> + { "rdctl-no", "on" }, >> + { "ibrs-all", "on" }, >> + { "skip-l1dfl-vmentry", "on" }, >> + { "mds-no", "on" }, >> + { "pschange-mc-no", "on" }, >> + { "taa-no", "on" }, >> + { /* end of list */ } >> + }, >> + }, >> { /* end of list */ } >> } >> }, >> -- >> 2.20.1 >> >>
On Mon, Mar 23, 2020 at 10:58:16AM +0800, Xiaoyao Li wrote: > On 3/23/2020 10:32 AM, Tao Xu wrote: > > Hi Xiaoyao, > > > > May be you can add .note for this new version. > > > > for example: > > > > + .version = 3, > > + .note = "ARCH_CAPABILITIES", > > + .props = (PropValue[]) { > > Hi Paolo and Eduardo, > > Need I spin a new version to add the .note ? > Maybe you can add it when queue? Please send a follow up patch so we don't hold a bug fix because of something that's just cosmetic. I will queue this patch. We still need a new version of "target/i386: Add notes for versioned CPU models"[1], don't we? [1] https://lore.kernel.org/qemu-devel/20200228215253.GB494511@habkost.net/
On 3/24/2020 2:39 AM, Eduardo Habkost wrote: > On Mon, Mar 23, 2020 at 10:58:16AM +0800, Xiaoyao Li wrote: >> On 3/23/2020 10:32 AM, Tao Xu wrote: >>> Hi Xiaoyao, >>> >>> May be you can add .note for this new version. >>> >>> for example: >>> >>> + .version = 3, >>> + .note = "ARCH_CAPABILITIES", >>> + .props = (PropValue[]) { >> >> Hi Paolo and Eduardo, >> >> Need I spin a new version to add the .note ? >> Maybe you can add it when queue? > > Please send a follow up patch so we don't hold a bug fix because > of something that's just cosmetic. I will queue this patch. We > still need a new version of "target/i386: Add notes for versioned > CPU models"[1], don't we? > > [1] https://lore.kernel.org/qemu-devel/20200228215253.GB494511@habkost.net/ > I am sorry for misunderstanding your comments in that patch[1]. I will submit a new version of this patch.
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 92fafa265914..5fba6a2ad6b3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3496,6 +3496,19 @@ static X86CPUDefinition builtin_x86_defs[] = { { /* end of list */ } }, }, + { + .version = 3, + .props = (PropValue[]) { + { "arch-capabilities", "on" }, + { "rdctl-no", "on" }, + { "ibrs-all", "on" }, + { "skip-l1dfl-vmentry", "on" }, + { "mds-no", "on" }, + { "pschange-mc-no", "on" }, + { "taa-no", "on" }, + { /* end of list */ } + }, + }, { /* end of list */ } } },
Current Icelake-Server CPU model lacks all the features enumerated by MSR_IA32_ARCH_CAPABILITIES. Add them, so that guest of "Icelake-Server" can see all of them. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> --- v2: - Add it as a new version. --- target/i386/cpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)