[03/13] usb: dwc3: meson-g12a: handle the phy and glue registers separately

Message ID	20200324102030.31000-4-narmstrong@baylibre.com (mailing list archive)
State	Superseded
Headers	show Return-Path: <SRS0=xPKD=5J=lists.infradead.org=linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 420A12080C From: Neil Armstrong <narmstrong@baylibre.com> To: kishon@ti.com, balbi@kernel.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com Subject: [PATCH 03/13] usb: dwc3: meson-g12a: handle the phy and glue registers separately Date: Tue, 24 Mar 2020 11:20:20 +0100 Message-Id: <20200324102030.31000-4-narmstrong@baylibre.com> In-Reply-To: <20200324102030.31000-1-narmstrong@baylibre.com> References: <20200324102030.31000-1-narmstrong@baylibre.com> MIME-Version: 1.0 summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:341 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid Precedence: list Cc: linux-amlogic@lists.infradead.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong <narmstrong@baylibre.com> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" <linux-amlogic-bounces@lists.infradead.org> Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org
Series	usb: dwc3: meson: add OTG support for GXL/GXM \| expand [00/13] usb: dwc3: meson: add OTG support for GXL/GXM [01/13] dt-bindings: usb: amlogic, meson-g12a-usb-ctrl: add the Amlogic GXL and GXM Families USB Gl… [02/13] usb: dwc3: meson-g12a: specify phy names in soc data [03/13] usb: dwc3: meson-g12a: handle the phy and glue registers separately [04/13] usb: dwc3: meson-g12a: get the reset as shared [05/13] usb: dwc3: meson-g12a: refactor usb2 phy init [06/13] usb: dwc3: meson-g12a: refactor usb init [07/13] usb: dwc3: meson-g12a: support the GXL/GXM DWC3 host phy disconnect [08/13] usb: dwc3: meson-g12a: add support for GXL and GXM SoCs [09/13] arm64: dts: amlogic: use the new USB control driver for GXL and GXM [10/13] phy: amlogic: meson-gxl-usb3: remove code for non-existing PHY [11/13] usb: dwc3: of-simple: remove Amlogic GXL and AXG compatibles [12/13] dt-bindings: usb: dwc3: remove amlogic compatible entries [13/13] dt-bindings: usb: amlogic, dwc3: remove old DWC3 wrapper

diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 7ba5fb3d0e22..f608ffb059b3 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -30,7 +30,7 @@ #include <linux/usb/role.h> #include <linux/regulator/consumer.h> -/* USB2 Ports Control Registers */ +/* USB2 Ports Control Registers, offsets are per-port */ #define U2P_REG_SIZE 0x20 @@ -50,14 +50,16 @@ /* USB Glue Control Registers */ -#define USB_R0 0x80 +#define G12A_GLUE_OFFSET 0x80 + +#define USB_R0 0x00 #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17) #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18) #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19) #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29) #define USB_R0_U2D_ACT BIT(31) -#define USB_R1 0x84 +#define USB_R1 0x04 #define USB_R1_U3H_BIGENDIAN_GS BIT(0) #define USB_R1_U3H_PME_ENABLE BIT(1) #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(4, 2) @@ -69,23 +71,23 @@ #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19) #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25) -#define USB_R2 0x88 +#define USB_R2 0x08 #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20) #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26) -#define USB_R3 0x8c +#define USB_R3 0x0c #define USB_R3_P30_SSC_ENABLE BIT(0) #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1) #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4) #define USB_R3_P30_REF_SSP_EN BIT(13) -#define USB_R4 0x90 +#define USB_R4 0x10 #define USB_R4_P21_PORT_RESET_0 BIT(0) #define USB_R4_P21_SLEEP_M0 BIT(1) #define USB_R4_MEM_PD_MASK GENMASK(3, 2) #define USB_R4_P21_ONLY BIT(4) -#define USB_R5 0x94 +#define USB_R5 0x14 #define USB_R5_ID_DIG_SYNC BIT(0) #define USB_R5_ID_DIG_REG BIT(1) #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2) @@ -117,20 +119,27 @@ static const char *meson_a1_phy_names[] = { "usb2-phy0", "usb2-phy1" }; +struct dwc3_meson_g12a; + struct dwc3_meson_g12a_drvdata { bool otg_switch_supported; struct clk_bulk_data *clks; int num_clks; const char **phy_names; int num_phys; + int (*setup_regmaps)(struct dwc3_meson_g12a *priv, void __iomem *base); }; +static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, + void __iomem *base); + static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .otg_switch_supported = true, .clks = meson_g12a_clocks, .num_clks = ARRAY_SIZE(meson_g12a_clocks), .phy_names = meson_g12a_phy_names, .num_phys = ARRAY_SIZE(meson_g12a_phy_names), + .setup_regmaps = dwc3_meson_g12a_setup_regmaps, }; static struct dwc3_meson_g12a_drvdata a1_drvdata = { @@ -139,11 +148,13 @@ static struct dwc3_meson_g12a_drvdata a1_drvdata = { .num_clks = ARRAY_SIZE(meson_a1_clocks), .phy_names = meson_a1_phy_names, .num_phys = ARRAY_SIZE(meson_a1_phy_names), + .setup_regmaps = dwc3_meson_g12a_setup_regmaps, }; struct dwc3_meson_g12a { struct device *dev; - struct regmap *regmap; + struct regmap *u2p_regmap[PHY_COUNT]; + struct regmap *usb_glue_regmap; struct reset_control *reset; struct phy *phys[PHY_COUNT]; enum usb_dr_mode otg_mode; @@ -160,11 +171,11 @@ static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv, int i, enum phy_mode mode) { if (mode == PHY_MODE_USB_HOST) - regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, U2P_R0_HOST_DEVICE, U2P_R0_HOST_DEVICE); else - regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, U2P_R0_HOST_DEVICE, 0); } @@ -184,13 +195,12 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) if (!strstr(priv->drvdata->phy_names[i], "usb2")) continue; - regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, U2P_R0_POWER_ON_RESET, U2P_R0_POWER_ON_RESET); if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) { - regmap_update_bits(priv->regmap, - U2P_R0 + (U2P_REG_SIZE * i), + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS, U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS); @@ -200,7 +210,7 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) dwc3_meson_g12a_usb2_set_mode(priv, i, PHY_MODE_USB_HOST); - regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), + regmap_update_bits(priv->u2p_regmap[i], U2P_R0, U2P_R0_POWER_ON_RESET, 0); } @@ -209,7 +219,7 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv) { - regmap_update_bits(priv->regmap, USB_R3, + regmap_update_bits(priv->usb_glue_regmap, USB_R3, USB_R3_P30_SSC_RANGE_MASK | USB_R3_P30_REF_SSP_EN, USB_R3_P30_SSC_ENABLE | @@ -217,21 +227,21 @@ static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv) USB_R3_P30_REF_SSP_EN); udelay(2); - regmap_update_bits(priv->regmap, USB_R2, + regmap_update_bits(priv->usb_glue_regmap, USB_R2, USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, 0x15)); - regmap_update_bits(priv->regmap, USB_R2, + regmap_update_bits(priv->usb_glue_regmap, USB_R2, USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, 0x20)); udelay(2); - regmap_update_bits(priv->regmap, USB_R1, + regmap_update_bits(priv->usb_glue_regmap, USB_R1, USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT, USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT); - regmap_update_bits(priv->regmap, USB_R1, + regmap_update_bits(priv->usb_glue_regmap, USB_R1, USB_R1_P30_PCS_TX_SWING_FULL_MASK, FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127)); } @@ -239,16 +249,16 @@ static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv) static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv) { if (priv->otg_phy_mode == PHY_MODE_USB_DEVICE) { - regmap_update_bits(priv->regmap, USB_R0, + regmap_update_bits(priv->usb_glue_regmap, USB_R0, USB_R0_U2D_ACT, USB_R0_U2D_ACT); - regmap_update_bits(priv->regmap, USB_R0, + regmap_update_bits(priv->usb_glue_regmap, USB_R0, USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0); - regmap_update_bits(priv->regmap, USB_R4, + regmap_update_bits(priv->usb_glue_regmap, USB_R4, USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0); } else { - regmap_update_bits(priv->regmap, USB_R0, + regmap_update_bits(priv->usb_glue_regmap, USB_R0, USB_R0_U2D_ACT, 0); - regmap_update_bits(priv->regmap, USB_R4, + regmap_update_bits(priv->usb_glue_regmap, USB_R4, USB_R4_P21_SLEEP_M0, 0); } } @@ -261,17 +271,17 @@ static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv) if (ret) return ret; - regmap_update_bits(priv->regmap, USB_R1, + regmap_update_bits(priv->usb_glue_regmap, USB_R1, USB_R1_U3H_FLADJ_30MHZ_REG_MASK, FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20)); - regmap_update_bits(priv->regmap, USB_R5, + regmap_update_bits(priv->usb_glue_regmap, USB_R5, USB_R5_ID_DIG_EN_0, USB_R5_ID_DIG_EN_0); - regmap_update_bits(priv->regmap, USB_R5, + regmap_update_bits(priv->usb_glue_regmap, USB_R5, USB_R5_ID_DIG_EN_1, USB_R5_ID_DIG_EN_1); - regmap_update_bits(priv->regmap, USB_R5, + regmap_update_bits(priv->usb_glue_regmap, USB_R5, USB_R5_ID_DIG_TH_MASK, FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff)); @@ -284,7 +294,8 @@ static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv) return 0; } -static const struct regmap_config phy_meson_g12a_usb3_regmap_conf = { +static const struct regmap_config phy_meson_g12a_usb_glue_regmap_conf = { + .name = "usb-glue", .reg_bits = 8, .val_bits = 32, .reg_stride = 4, @@ -321,7 +332,7 @@ static enum phy_mode dwc3_meson_g12a_get_id(struct dwc3_meson_g12a *priv) { u32 reg; - regmap_read(priv->regmap, USB_R5, &reg); + regmap_read(priv->usb_glue_regmap, USB_R5, &reg); if (reg & (USB_R5_ID_DIG_SYNC | USB_R5_ID_DIG_REG)) return PHY_MODE_USB_DEVICE; @@ -396,7 +407,8 @@ static irqreturn_t dwc3_meson_g12a_irq_thread(int irq, void *data) dev_warn(priv->dev, "Failed to switch OTG mode\n"); } - regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_IRQ, 0); + regmap_update_bits(priv->usb_glue_regmap, USB_R5, + USB_R5_ID_DIG_IRQ, 0); return IRQ_HANDLED; } @@ -431,7 +443,7 @@ static int dwc3_meson_g12a_otg_init(struct platform_device *pdev, if (priv->otg_mode == USB_DR_MODE_OTG) { /* Ack irq before registering */ - regmap_update_bits(priv->regmap, USB_R5, + regmap_update_bits(priv->usb_glue_regmap, USB_R5, USB_R5_ID_DIG_IRQ, 0); irq = platform_get_irq(pdev, 0); @@ -466,6 +478,41 @@ static int dwc3_meson_g12a_otg_init(struct platform_device *pdev, return 0; } +static int dwc3_meson_g12a_setup_regmaps(struct dwc3_meson_g12a *priv, + void __iomem *base) +{ + int i; + + priv->usb_glue_regmap = devm_regmap_init_mmio(priv->dev, + base + G12A_GLUE_OFFSET, + &phy_meson_g12a_usb_glue_regmap_conf); + if (IS_ERR(priv->usb_glue_regmap)) + return PTR_ERR(priv->usb_glue_regmap); + + /* Create a regmap for each USB2 PHY control register set */ + for (i = 0; i < priv->usb2_ports; i++) { + struct regmap_config u2p_regmap_config = { + .reg_bits = 8, + .val_bits = 32, + .reg_stride = 4, + .max_register = U2P_R1, + }; + + u2p_regmap_config.name = devm_kasprintf(priv->dev, GFP_KERNEL, + "u2p-%d", i); + if (!u2p_regmap_config.name) + return -ENOMEM; + + priv->u2p_regmap[i] = devm_regmap_init_mmio(priv->dev, + base + (i * U2P_REG_SIZE), + &u2p_regmap_config); + if (IS_ERR(priv->u2p_regmap[i])) + return PTR_ERR(priv->u2p_regmap[i]); + } + + return 0; +} + static int dwc3_meson_g12a_probe(struct platform_device *pdev) { struct dwc3_meson_g12a *priv; @@ -482,10 +529,12 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); - priv->regmap = devm_regmap_init_mmio(dev, base, - &phy_meson_g12a_usb3_regmap_conf); - if (IS_ERR(priv->regmap)) - return PTR_ERR(priv->regmap); + priv->drvdata = of_device_get_match_data(&pdev->dev); + + priv->dev = dev; + ret = priv->drvdata->setup_regmaps(priv, base); + if (ret) + return ret; priv->vbus = devm_regulator_get_optional(dev, "vbus"); if (IS_ERR(priv->vbus)) { @@ -494,8 +543,6 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) priv->vbus = NULL; } - priv->drvdata = of_device_get_match_data(&pdev->dev); - ret = devm_clk_bulk_get(dev, priv->drvdata->num_clks, priv->drvdata->clks); @@ -508,7 +555,6 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) return ret; platform_set_drvdata(pdev, priv); - priv->dev = dev; priv->reset = devm_reset_control_get(dev, NULL); if (IS_ERR(priv->reset)) {

[03/13] usb: dwc3: meson-g12a: handle the phy and glue registers separately

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