| Message ID | 20200312053841.2794-8-vandita.kulkarni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for mipi dsi cmd mode | expand |
On Thu, 12 Mar 2020, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote: > In case of dual link, we get the TE on slave. > So clear the TE on slave DSI IIR. > > v2: Pass only relevant masked bits to the handler (Jani) > > v3: Fix the check for cmd mode in TE handler function. > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 64 +++++++++++++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 89489a247276..2e1418515c9f 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2262,6 +2262,62 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) > drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n"); > } > > +void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, > + u32 te_trigger) > +{ > + enum pipe pipe = INVALID_PIPE; > + enum transcoder dsi_trans; > + enum port port; > + u32 val, tmp; > + > + /* > + * Incase of dual link, TE comes from DSI_1 > + * this is to check if dual link is enabled > + */ > + val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0)); > + val &= PORT_SYNC_MODE_ENABLE; > + > + /* > + * if dual link is enabled, then read DSI_0 > + * transcoder registers > + */ > + port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ? > + PORT_A : PORT_B; > + dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; > + > + /* Check if DSI configured in command mode */ > + val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)); > + val = val & OP_MODE_MASK; > + > + if ((val != CMD_MODE_NO_GATE) && (val != CMD_MODE_TE_GATE)) { > + DRM_ERROR("DSI trancoder not configured in command mode\n"); drm_err() > + return; > + } > + > + /* Get PIPE for handling VBLANK event */ > + val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); > + switch (val & TRANS_DDI_EDP_INPUT_MASK) { > + case TRANS_DDI_EDP_INPUT_A_ON: > + pipe = PIPE_A; > + break; > + case TRANS_DDI_EDP_INPUT_B_ONOFF: > + pipe = PIPE_B; > + break; > + case TRANS_DDI_EDP_INPUT_C_ONOFF: > + pipe = PIPE_C; > + break; > + default: > + DRM_ERROR("Invalid PIPE\n"); drm_err()... but don't want to pass INVALID_PIPE to intel_handle_vblank() below. > + } > + > + /* clear TE in dsi IIR */ > + port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; > + tmp = I915_READ(DSI_INTR_IDENT_REG(port)); > + I915_WRITE(DSI_INTR_IDENT_REG(port), tmp); > + > + drm_handle_vblank(&dev_priv->drm, pipe); Please use intel_handle_vblank(). It takes into account pipe might not match crtc index. > +} > + > static irqreturn_t > gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) > { > @@ -2328,6 +2384,14 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) > found = true; > } > > + if (INTEL_GEN(dev_priv) >= 11) { > + tmp_mask = iir & (DSI0_TE | DSI1_TE); > + if (tmp_mask) { > + gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask); > + found = true; > + } > + } > + > if (!found) > drm_err(&dev_priv->drm, > "Unexpected DE Port interrupt\n");
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 89489a247276..2e1418515c9f 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2262,6 +2262,62 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n"); } +void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, + u32 te_trigger) +{ + enum pipe pipe = INVALID_PIPE; + enum transcoder dsi_trans; + enum port port; + u32 val, tmp; + + /* + * Incase of dual link, TE comes from DSI_1 + * this is to check if dual link is enabled + */ + val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0)); + val &= PORT_SYNC_MODE_ENABLE; + + /* + * if dual link is enabled, then read DSI_0 + * transcoder registers + */ + port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ? + PORT_A : PORT_B; + dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; + + /* Check if DSI configured in command mode */ + val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)); + val = val & OP_MODE_MASK; + + if ((val != CMD_MODE_NO_GATE) && (val != CMD_MODE_TE_GATE)) { + DRM_ERROR("DSI trancoder not configured in command mode\n"); + return; + } + + /* Get PIPE for handling VBLANK event */ + val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); + switch (val & TRANS_DDI_EDP_INPUT_MASK) { + case TRANS_DDI_EDP_INPUT_A_ON: + pipe = PIPE_A; + break; + case TRANS_DDI_EDP_INPUT_B_ONOFF: + pipe = PIPE_B; + break; + case TRANS_DDI_EDP_INPUT_C_ONOFF: + pipe = PIPE_C; + break; + default: + DRM_ERROR("Invalid PIPE\n"); + } + + /* clear TE in dsi IIR */ + port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; + tmp = I915_READ(DSI_INTR_IDENT_REG(port)); + I915_WRITE(DSI_INTR_IDENT_REG(port), tmp); + + drm_handle_vblank(&dev_priv->drm, pipe); +} + static irqreturn_t gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) { @@ -2328,6 +2384,14 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) found = true; } + if (INTEL_GEN(dev_priv) >= 11) { + tmp_mask = iir & (DSI0_TE | DSI1_TE); + if (tmp_mask) { + gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask); + found = true; + } + } + if (!found) drm_err(&dev_priv->drm, "Unexpected DE Port interrupt\n");
In case of dual link, we get the TE on slave. So clear the TE on slave DSI IIR. v2: Pass only relevant masked bits to the handler (Jani) v3: Fix the check for cmd mode in TE handler function. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 64 +++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+)