diff mbox

[RFC,06/12] arm/dt: Tegra: Add pinmux node

Message ID 1313189697-21287-7-git-send-email-swarren@nvidia.com (mailing list archive)
State New, archived
Headers show

Commit Message

Stephen Warren Aug. 12, 2011, 10:54 p.m. UTC 
Add a pinmux node to tegra20.dtsi in order to instantiate the future
pinmux device. Add pinmux nodes to Harmony and Seaboard, which detail
the entire default pinmux configuration. This configuration is identical
to that in board-harmony/seaboard-pinmux.c.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/boot/dts/tegra-harmony.dts  |  464 ++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra-seaboard.dts |  401 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra20.dtsi       |    5 +
 3 files changed, 870 insertions(+), 0 deletions(-)

Comments

Olof Johansson Aug. 14, 2011, 7:24 a.m. UTC | #1 
Hi,

On Fri, Aug 12, 2011 at 3:54 PM, Stephen Warren <swarren@nvidia.com> wrote:
> Add a pinmux node to tegra20.dtsi in order to instantiate the future
> pinmux device. Add pinmux nodes to Harmony and Seaboard, which detail
> the entire default pinmux configuration. This configuration is identical
> to that in board-harmony/seaboard-pinmux.c.

Again, documentation for the binding is needed.

Seeing the table coded up now though, I wonder if it could make sense
to flip it around? The number of functions multiplexed out are fewer
than the pin groups (and this would be even more true on platforms
that have per-pin configurations and/or smaller groups).

I.e. something like:

    sdio4 {
            nvidia,pingroups = < DTA DTD >; // Not sure how to
reference this though -- integers would be hard to read. DTA/DTD
aren't valid values in the syntax.
            nvidia,pull-up
    },

And any pingroups not covered by a function would be left alone (one
could easily define a few no-op functions to set pull up/down and
tristate values on the unused groups).

[...]

> +       pinmux: pinmux@70000000 {
> +               ATA {

I would prefer seeing these in lower case (since device tree tends to
be no-caps). Should be easy to switch to strcasecmp in the code.

[...]
> +               CDEV2 {
> +                       nvidia,function = "PLLP_OUT4";

The string here is a bit unfortunate. It's really just used to map
from the string to an integer anyway, with the reverse mapping being
produced by the debugfs output. But especially if the function is
flipped above, the different pingroups referenced might not use the
same value for each function, so some sort of lookup will still be
needed. Not much to do about, it seems. :(


> +                       nvidia,pull = "down";

This should be done by discrete properties instead: nvidia,pull-up,
nvidia-pull-down (and omitted means normal), without values.


-Olof
Stephen Warren Aug. 15, 2011, 4:41 p.m. UTC | #2 
Olof Johansson wrote at Sunday, August 14, 2011 1:25 AM:
> On Fri, Aug 12, 2011 at 3:54 PM, Stephen Warren <swarren@nvidia.com> wrote:
> > Add a pinmux node to tegra20.dtsi in order to instantiate the future
> > pinmux device. Add pinmux nodes to Harmony and Seaboard, which detail
> > the entire default pinmux configuration. This configuration is identical
> > to that in board-harmony/seaboard-pinmux.c.
> 
> Again, documentation for the binding is needed.

Yes. It should have been there, but I screwed up.

> Seeing the table coded up now though, I wonder if it could make sense
> to flip it around? The number of functions multiplexed out are fewer
> than the pin groups (and this would be even more true on platforms
> that have per-pin configurations and/or smaller groups).

There are 116 pin groups and 61 functions, so this certainly would reduce
the size of the tree.

> I.e. something like:
> 
>     sdio4 {
>             nvidia,pingroups = < DTA DTD >; // Not sure how to
> reference this though -- integers would be hard to read. DTA/DTD
> aren't valid values in the syntax.
>             nvidia,pull-up
>     },
> 
> And any pingroups not covered by a function would be left alone

I'm personally inclined not to do this.

a) The HW registers are laid out such that each pingroup has various
properties, so the current binding represents that directly. That said,
inverting the table would contain exactly the same data, so this argument
is slightly tenuous/arbitrary, except that:

b) I think we'd still need tristate and pull properties per pin-group
either way; within a given special function, I see no reason for every
pingroup to need the same pull/tristate values (otherwise, I imagine the
Tegra HW designers would have lumped all the pins into a single pingroup
already). For example, an interface with data and control signals might
need pullups on control signals, but none on data.

c) Similar to that, a RSVD/NONE (or otherwise unused) function might be
used for a bunch of pingroups that are in fact used by GPIOs, and hence
only the pull/tristate values are relevant, since the GPIO controller
will actually control the data on the line. In this case, there's no 
reason to assume that different pingroups that have the same function are
related in any way, and hence should have the same pull/tristate.

Given, b/c, we'd need an array of pull/tristate values per pingroup within
a given function, and I think the syntax for that would be sufficiently
complex that the binding in the current patchset makes more sense.

Do you agree?

> (one
> could easily define a few no-op functions to set pull up/down and
> tristate values on the unused groups).

The binding (and original pinmux code) does define RSVD1/2/3/4 functions
for the case where a pingroup should be programmed to an unused/quiescent
state. There's also a NONE function for the pingroups that don't support
muxing, but just pullup/down and tristate.

> [...]
> 
> > +       pinmux: pinmux@70000000 {
> > +               ATA {
> 
> I would prefer seeing these in lower case (since device tree tends to
> be no-caps). Should be easy to switch to strcasecmp in the code.

Sure.

> [...]
> > +               CDEV2 {
> > +                       nvidia,function = "PLLP_OUT4";
> 
> The string here is a bit unfortunate. It's really just used to map
> from the string to an integer anyway, with the reverse mapping being
> produced by the debugfs output. But especially if the function is
> flipped above, the different pingroups referenced might not use the
> same value for each function, so some sort of lookup will still be
> needed. Not much to do about, it seems. :(

I originally considered syntax like:

    nvidia,function = <33>; // PLLP_OUT4

However, I figured this was problematic because:

a) Calculating the integers would be problematic; pinmux.h doesn't
currently list the integer for each value in enum tegra_mux_func, although
I suppose it and the binding documentation could easily be modified to do
so.

b) With just an integer, it's much harder to know what the value means.

c) With both the integer and comment, they can get out of sync if
incorrectly edited.

I'd be much more included to use integers if the *.dts files wer run
though the pre-processor, and hence defines could be used. I do observe
that Documentation/devicetree/booting-without-of.txt says:

    It is also suggested that you pipe your source file through cpp (gcc
    preprocessor) so you can use #include's, #define for constants, etc...

> > +                       nvidia,pull = "down";
> 
> This should be done by discrete properties instead: nvidia,pull-up,
> nvidia-pull-down (and omitted means normal), without values.

OK.
diff mbox

Patch

diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index c9bb847..066a338 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -30,6 +30,470 @@ 
 		>;
 	};
 
+	pinmux: pinmux@70000000 {
+		ATA {
+			nvidia,function = "IDE";
+		};
+		ATB {
+			nvidia,function = "SDIO4";
+		};
+		ATC {
+			nvidia,function = "NAND";
+		};
+		ATD {
+			nvidia,function = "GMI";
+		};
+		ATE {
+			nvidia,function = "GMI";
+		};
+		CDEV1 {
+			nvidia,function = "PLLA_OUT";
+		};
+		CDEV2 {
+			nvidia,function = "PLLP_OUT4";
+			nvidia,pull = "down";
+			nvidia,tristate;
+		};
+		CRTP {
+			nvidia,function = "CRT";
+			nvidia,tristate;
+		};
+		CSUS {
+			nvidia,function = "VI_SENSOR_CLK";
+			nvidia,pull = "down";
+			nvidia,tristate;
+		};
+		DAP1 {
+			nvidia,function = "DAP1";
+		};
+		DAP2 {
+			nvidia,function = "DAP2";
+			nvidia,tristate;
+		};
+		DAP3 {
+			nvidia,function = "DAP3";
+			nvidia,tristate;
+		};
+		DAP4 {
+			nvidia,function = "DAP4";
+			nvidia,tristate;
+		};
+		DDC {
+			nvidia,function = "I2C2";
+			nvidia,pull = "up";
+		};
+		DTA {
+			nvidia,function = "SDIO2";
+			nvidia,pull = "up";
+		};
+		DTB {
+			nvidia,function = "RSVD1";
+		};
+		DTC {
+			nvidia,function = "RSVD1";
+			nvidia,tristate;
+		};
+		DTD {
+			nvidia,function = "SDIO2";
+			nvidia,pull = "up";
+		};
+		DTE {
+			nvidia,function = "RSVD1";
+			nvidia,tristate;
+		};
+		DTF {
+			nvidia,function = "I2C3";
+			nvidia,tristate;
+		};
+		GMA {
+			nvidia,function = "SDIO4";
+		};
+		GMB {
+			nvidia,function = "GMI";
+		};
+		GMC {
+			nvidia,function = "UARTD";
+		};
+		GMD {
+			nvidia,function = "GMI";
+		};
+		GME {
+			nvidia,function = "SDIO4";
+		};
+		GPU {
+			nvidia,function = "GMI";
+			nvidia,tristate;
+		};
+		GPU7 {
+			nvidia,function = "RTCK";
+		};
+		GPV {
+			nvidia,function = "PCIE";
+			nvidia,tristate;
+		};
+		HDINT {
+			nvidia,function = "HDMI";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		I2CP {
+			nvidia,function = "I2C";
+		};
+		IRRX {
+			nvidia,function = "UARTA";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		IRTX {
+			nvidia,function = "UARTA";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		KBCA {
+			nvidia,function = "KBC";
+			nvidia,pull = "up";
+		};
+		KBCB {
+			nvidia,function = "KBC";
+			nvidia,pull = "up";
+		};
+		KBCC {
+			nvidia,function = "KBC";
+			nvidia,pull = "up";
+		};
+		KBCD {
+			nvidia,function = "KBC";
+			nvidia,pull = "up";
+		};
+		KBCE {
+			nvidia,function = "KBC";
+			nvidia,pull = "up";
+		};
+		KBCF {
+			nvidia,function = "KBC";
+			nvidia,pull = "up";
+		};
+		LCSN {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		LD0 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD1 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD10 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD11 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD12 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD13 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD14 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD15 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD16 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD17 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD2 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD3 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD4 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD5 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD6 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD7 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD8 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LD9 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LDC {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		LDI {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LHP0 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LHP1 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LHP2 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LHS {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+		};
+		LM0 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+		};
+		LM1 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		LPP {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LPW0 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+		};
+		LPW1 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		LPW2 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+		};
+		LSC0 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+		};
+		LSC1 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		LSCK {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		LSDA {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		LSDI {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		LSPI {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+		};
+		LVP0 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		LVP1 {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "down";
+		};
+		LVS {
+			nvidia,function = "DISPLAYA";
+			nvidia,pull = "up";
+		};
+		OWC {
+			nvidia,function = "RSVD2";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		PMC {
+			nvidia,function = "PWR_ON";
+		};
+		PTA {
+			nvidia,function = "HDMI";
+		};
+		RM {
+			nvidia,function = "I2C";
+		};
+		SDB {
+			nvidia,function = "PWM";
+			nvidia,tristate;
+		};
+		SDC {
+			nvidia,function = "PWM";
+			nvidia,pull = "up";
+		};
+		SDD {
+			nvidia,function = "PWM";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		SDIO1 {
+			nvidia,function = "SDIO1";
+			nvidia,tristate;
+		};
+		SLXA {
+			nvidia,function = "PCIE";
+			nvidia,tristate;
+		};
+		SLXC {
+			nvidia,function = "SPDIF";
+			nvidia,tristate;
+		};
+		SLXD {
+			nvidia,function = "SPDIF";
+			nvidia,tristate;
+		};
+		SLXK {
+			nvidia,function = "PCIE";
+			nvidia,tristate;
+		};
+		SPDI {
+			nvidia,function = "RSVD2";
+			nvidia,tristate;
+		};
+		SPDO {
+			nvidia,function = "RSVD2";
+			nvidia,tristate;
+		};
+		SPIA {
+			nvidia,function = "GMI";
+		};
+		SPIB {
+			nvidia,function = "GMI";
+		};
+		SPIC {
+			nvidia,function = "GMI";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		SPID {
+			nvidia,function = "SPI1";
+			nvidia,pull = "down";
+			nvidia,tristate;
+		};
+		SPIE {
+			nvidia,function = "SPI1";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		SPIF {
+			nvidia,function = "SPI1";
+			nvidia,pull = "down";
+			nvidia,tristate;
+		};
+		SPIG {
+			nvidia,function = "SPI2_ALT";
+			nvidia,tristate;
+		};
+		SPIH {
+			nvidia,function = "SPI2_ALT";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		UAA {
+			nvidia,function = "ULPI";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		UAB {
+			nvidia,function = "ULPI";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		UAC {
+			nvidia,function = "RSVD2";
+			nvidia,tristate;
+		};
+		UAD {
+			nvidia,function = "IRDA";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		UCA {
+			nvidia,function = "UARTC";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		UCB {
+			nvidia,function = "UARTC";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		UDA {
+			nvidia,function = "ULPI";
+			nvidia,tristate;
+		};
+		CK32 {
+			nvidia,function = "NONE";
+		};
+		DDRC {
+			nvidia,function = "NONE";
+		};
+		PMCA {
+			nvidia,function = "NONE";
+		};
+		PMCB {
+			nvidia,function = "NONE";
+		};
+		PMCC {
+			nvidia,function = "NONE";
+		};
+		PMCD {
+			nvidia,function = "NONE";
+		};
+		PMCE {
+			nvidia,function = "NONE";
+		};
+		XM2C {
+			nvidia,function = "NONE";
+		};
+		XM2D {
+			nvidia,function = "NONE";
+		};
+	};
+
 	i2c@7000c000 {
 		clock-frequency = <400000>;
 
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index b0d44a5..7ac3ab3 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -24,6 +24,407 @@ 
 		>;
 	};
 
+	pinmux: pinmux@70000000 {
+		ATA {
+			nvidia,function = "IDE";
+		};
+		ATB {
+			nvidia,function = "SDIO4";
+		};
+		ATC {
+			nvidia,function = "NAND";
+		};
+		ATD {
+			nvidia,function = "GMI";
+		};
+		ATE {
+			nvidia,function = "GMI";
+			nvidia,tristate;
+		};
+		CDEV1 {
+			nvidia,function = "PLLA_OUT";
+		};
+		CDEV2 {
+			nvidia,function = "PLLP_OUT4";
+		};
+		CRTP {
+			nvidia,function = "CRT";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		CSUS {
+			nvidia,function = "VI_SENSOR_CLK";
+			nvidia,tristate;
+		};
+		DAP1 {
+			nvidia,function = "DAP1";
+		};
+		DAP2 {
+			nvidia,function = "DAP2";
+		};
+		DAP3 {
+			nvidia,function = "DAP3";
+			nvidia,tristate;
+		};
+		DAP4 {
+			nvidia,function = "DAP4";
+		};
+		DDC {
+			nvidia,function = "RSVD2";
+			nvidia,tristate;
+		};
+		DTA {
+			nvidia,function = "VI";
+			nvidia,pull = "down";
+		};
+		DTB {
+			nvidia,function = "VI";
+			nvidia,pull = "down";
+		};
+		DTC {
+			nvidia,function = "VI";
+			nvidia,pull = "down";
+		};
+		DTD {
+			nvidia,function = "VI";
+			nvidia,pull = "down";
+		};
+		DTE {
+			nvidia,function = "VI";
+			nvidia,pull = "down";
+			nvidia,tristate;
+		};
+		DTF {
+			nvidia,function = "I2C3";
+		};
+		GMA {
+			nvidia,function = "SDIO4";
+		};
+		GMB {
+			nvidia,function = "GMI";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		GMC {
+			nvidia,function = "UARTD";
+		};
+		GMD {
+			nvidia,function = "SFLASH";
+		};
+		GME {
+			nvidia,function = "SDIO4";
+		};
+		GPU {
+			nvidia,function = "PWM";
+		};
+		GPU7 {
+			nvidia,function = "RTCK";
+		};
+		GPV {
+			nvidia,function = "PCIE";
+			nvidia,tristate;
+		};
+		HDINT {
+			nvidia,function = "HDMI";
+			nvidia,tristate;
+		};
+		I2CP {
+			nvidia,function = "I2C";
+		};
+		IRRX {
+			nvidia,function = "UARTB";
+		};
+		IRTX {
+			nvidia,function = "UARTB";
+		};
+		KBCA {
+			nvidia,function = "KBC";
+			nvidia,pull = "up";
+		};
+		KBCB {
+			nvidia,function = "KBC";
+			nvidia,pull = "up";
+		};
+		KBCC {
+			nvidia,function = "KBC";
+			nvidia,pull = "up";
+		};
+		KBCD {
+			nvidia,function = "KBC";
+			nvidia,pull = "up";
+		};
+		KBCE {
+			nvidia,function = "KBC";
+			nvidia,pull = "up";
+		};
+		KBCF {
+			nvidia,function = "KBC";
+			nvidia,pull = "up";
+		};
+		LCSN {
+			nvidia,function = "RSVD4";
+			nvidia,tristate;
+		};
+		LD0 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD1 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD10 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD11 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD12 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD13 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD14 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD15 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD16 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD17 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD2 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD3 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD4 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD5 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD6 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD7 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD8 {
+			nvidia,function = "DISPLAYA";
+		};
+		LD9 {
+			nvidia,function = "DISPLAYA";
+		};
+		LDC {
+			nvidia,function = "RSVD4";
+			nvidia,tristate;
+		};
+		LDI {
+			nvidia,function = "DISPLAYA";
+		};
+		LHP0 {
+			nvidia,function = "DISPLAYA";
+		};
+		LHP1 {
+			nvidia,function = "DISPLAYA";
+		};
+		LHP2 {
+			nvidia,function = "DISPLAYA";
+		};
+		LHS {
+			nvidia,function = "DISPLAYA";
+		};
+		LM0 {
+			nvidia,function = "RSVD4";
+		};
+		LM1 {
+			nvidia,function = "CRT";
+			nvidia,tristate;
+		};
+		LPP {
+			nvidia,function = "DISPLAYA";
+		};
+		LPW0 {
+			nvidia,function = "HDMI";
+		};
+		LPW1 {
+			nvidia,function = "RSVD4";
+			nvidia,tristate;
+		};
+		LPW2 {
+			nvidia,function = "HDMI";
+		};
+		LSC0 {
+			nvidia,function = "DISPLAYA";
+		};
+		LSC1 {
+			nvidia,function = "HDMI";
+			nvidia,tristate;
+		};
+		LSCK {
+			nvidia,function = "HDMI";
+			nvidia,tristate;
+		};
+		LSDA {
+			nvidia,function = "HDMI";
+			nvidia,tristate;
+		};
+		LSDI {
+			nvidia,function = "RSVD4";
+			nvidia,tristate;
+		};
+		LSPI {
+			nvidia,function = "DISPLAYA";
+		};
+		LVP0 {
+			nvidia,function = "RSVD4";
+			nvidia,tristate;
+		};
+		LVP1 {
+			nvidia,function = "DISPLAYA";
+		};
+		LVS {
+			nvidia,function = "DISPLAYA";
+		};
+		OWC {
+			nvidia,function = "RSVD2";
+			nvidia,tristate;
+		};
+		PMC {
+			nvidia,function = "PWR_ON";
+		};
+		PTA {
+			nvidia,function = "HDMI";
+		};
+		RM {
+			nvidia,function = "I2C";
+		};
+		SDB {
+			nvidia,function = "SDIO3";
+		};
+		SDC {
+			nvidia,function = "SDIO3";
+		};
+		SDD {
+			nvidia,function = "SDIO3";
+		};
+		SDIO1 {
+			nvidia,function = "SDIO1";
+			nvidia,pull = "up";
+		};
+		SLXA {
+			nvidia,function = "PCIE";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		SLXC {
+			nvidia,function = "SPDIF";
+			nvidia,tristate;
+		};
+		SLXD {
+			nvidia,function = "SPDIF";
+		};
+		SLXK {
+			nvidia,function = "PCIE";
+		};
+		SPDI {
+			nvidia,function = "RSVD2";
+		};
+		SPDO {
+			nvidia,function = "RSVD2";
+		};
+		SPIA {
+			nvidia,function = "GMI";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		SPIB {
+			nvidia,function = "GMI";
+			nvidia,tristate;
+		};
+		SPIC {
+			nvidia,function = "GMI";
+			nvidia,pull = "up";
+		};
+		SPID {
+			nvidia,function = "SPI1";
+			nvidia,tristate;
+		};
+		SPIE {
+			nvidia,function = "SPI1";
+			nvidia,tristate;
+		};
+		SPIF {
+			nvidia,function = "SPI1";
+			nvidia,pull = "down";
+			nvidia,tristate;
+		};
+		SPIG {
+			nvidia,function = "SPI2_ALT";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		SPIH {
+			nvidia,function = "SPI2_ALT";
+			nvidia,pull = "up";
+			nvidia,tristate;
+		};
+		UAA {
+			nvidia,function = "ULPI";
+			nvidia,pull = "up";
+		};
+		UAB {
+			nvidia,function = "ULPI";
+			nvidia,pull = "up";
+		};
+		UAC {
+			nvidia,function = "RSVD2";
+		};
+		UAD {
+			nvidia,function = "IRDA";
+		};
+		UCA {
+			nvidia,function = "UARTC";
+		};
+		UCB {
+			nvidia,function = "UARTC";
+		};
+		UDA {
+			nvidia,function = "ULPI";
+		};
+		CK32 {
+			nvidia,function = "NONE";
+		};
+		DDRC {
+			nvidia,function = "NONE";
+		};
+		PMCA {
+			nvidia,function = "NONE";
+		};
+		PMCB {
+			nvidia,function = "NONE";
+		};
+		PMCC {
+			nvidia,function = "NONE";
+		};
+		PMCD {
+			nvidia,function = "NONE";
+		};
+		PMCE {
+			nvidia,function = "NONE";
+		};
+		XM2C {
+			nvidia,function = "NONE";
+		};
+		XM2D {
+			nvidia,function = "NONE";
+		};
+	};
+
 	serial@70006300 {
 		clock-frequency = < 216000000 >;
 	};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 5727595..5921c1d 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -77,6 +77,11 @@ 
 		gpio-controller;
 	};
 
+	pinmux: pinmux@70000000 {
+		compatible = "nvidia,tegra20-pinmux";
+		reg = < 0x70000000 0xc00 >;
+	};
+
 	serial@70006000 {
 		compatible = "nvidia,tegra20-uart";
 		reg = <0x70006000 0x40>;