| Message ID | 20200413041709.3630-1-christophe.jaillet@wanadoo.fr (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | cdfdeb4a381d97d441ac421a86a2e8158346ad51 |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | clk: renesas: r9a06g032: Fix some typo in comments | expand |
On Mon, Apr 13, 2020 at 5:12 PM Christophe JAILLET <christophe.jaillet@wanadoo.fr> wrote: > This file seems to be for R9A06G032 only. So replace reference to > R9A09G032 by R9A06G032 to avoid confusion. > > AFAIK, R9A09G032 does'nt exist. > > Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in clk-renesas-for-v5.8. Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 1907ee195a08..d900f6bf53d0 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * R9A09G032 clock driver + * R9A06G032 clock driver * * Copyright (C) 2018 Renesas Electronics Europe Limited * @@ -338,8 +338,8 @@ clk_rdesc_get(struct r9a06g032_priv *clocks, } /* - * This implements the R9A09G032 clock gate 'driver'. We cannot use the system's - * clock gate framework as the gates on the R9A09G032 have a special enabling + * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's + * clock gate framework as the gates on the R9A06G032 have a special enabling * sequence, therefore we use this little proxy. */ struct r9a06g032_clk_gate {
This file seems to be for R9A06G032 only. So replace reference to R9A09G032 by R9A06G032 to avoid confusion. AFAIK, R9A09G032 does'nt exist. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> --- drivers/clk/renesas/r9a06g032-clocks.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)