drm/amd/display: Fix pageflip event race condition for DCN. (v2)

Commit Message

Mario Kleiner March 5, 2020, 9:20 p.m. UTC

Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
events at vsartup for DCN")' introduces a new way of pageflip
completion handling for DCN, and some trouble.

The current implementation introduces a race condition, which
can cause pageflip completion events to be sent out one vblank
too early, thereby confusing userspace and causing flicker:

prepare_flip_isr():

1. Pageflip programming takes the ddev->event_lock.
2. Sets acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED
3. Releases ddev->event_lock.

--> Deadline for surface address regs double-buffering passes on
    target pipe.

4. dc_commit_updates_for_stream() MMIO programs the new pageflip
   into hw, but too late for current vblank.

=> pflip_status == AMDGPU_FLIP_SUBMITTED, but flip won't complete
   in current vblank due to missing the double-buffering deadline
   by a tiny bit.

5. VSTARTUP trigger point in vblank is reached, VSTARTUP irq fires,
   dm_dcn_crtc_high_irq() gets called.

6. Detects pflip_status == AMDGPU_FLIP_SUBMITTED and assumes the
   pageflip has been completed/will complete in this vblank and
   sends out pageflip completion event to userspace and resets
   pflip_status = AMDGPU_FLIP_NONE.

=> Flip completion event sent out one vblank too early.

This behaviour has been observed during my testing with measurement
hardware a couple of time.

The commit message says that the extra flip event code was added to
dm_dcn_crtc_high_irq() to prevent missing to send out pageflip events
in case the pflip irq doesn't fire, because the "DCH HUBP" component
is clock gated and doesn't fire pflip irqs in that state. Also that
this clock gating may happen if no planes are active. According to
Nicholas, the clock gating can also happen if psr is active, and the
gating is controlled independently by the hardware, so difficult to
detect if and when the completion code in above commit is needed.

This patch tries the following solution: It only executes the extra pflip
completion code in dm_dcn_crtc_high_irq() iff the hardware reports
that there aren't any surface updated pending in the double-buffered
surface scanout address registers. Otherwise it leaves pflip completion
to the pflip irq handler, for a more race-free experience.

This would only guard against the order of events mentioned above.
If Step 5 (VSTARTUP trigger) happens before step 4 then this won't help
at all, because 1-3 + 5 might happen even without the hw being programmed
at all, ie. no surface update pending because none yet programmed into hw.

Therefore this patch also changes locking in amdgpu_dm_commit_planes(),
so that prepare_flip_isr() and dc_commit_updates_for_stream() are done
under event_lock protection within the same critical section.

v2: Take Nicholas comments into account, try a different solution.

Lightly tested on Polaris (locking) and Raven (the whole DCN stuff).
Seems to work without causing obvious new trouble.

Fixes: 16f17eda8bad ("drm/amd/display: Send vblank and user events at vsartup for DCN")
Signed-off-by: Mario Kleiner <[e-mail]>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 80 ++++++++++++++++---
 1 file changed, 67 insertions(+), 13 deletions(-)

Comments

Alex Deucher March 12, 2020, 2:32 p.m. UTC | #1

On Thu, Mar 5, 2020 at 4:21 PM Mario Kleiner <[e-mail]> wrote:
>
> Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
> events at vsartup for DCN")' introduces a new way of pageflip
> completion handling for DCN, and some trouble.
>
> The current implementation introduces a race condition, which
> can cause pageflip completion events to be sent out one vblank
> too early, thereby confusing userspace and causing flicker:
>
> prepare_flip_isr():
>
> 1. Pageflip programming takes the ddev->event_lock.
> 2. Sets acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED
> 3. Releases ddev->event_lock.
>
> --> Deadline for surface address regs double-buffering passes on
>     target pipe.
>
> 4. dc_commit_updates_for_stream() MMIO programs the new pageflip
>    into hw, but too late for current vblank.
>
> => pflip_status == AMDGPU_FLIP_SUBMITTED, but flip won't complete
>    in current vblank due to missing the double-buffering deadline
>    by a tiny bit.
>
> 5. VSTARTUP trigger point in vblank is reached, VSTARTUP irq fires,
>    dm_dcn_crtc_high_irq() gets called.
>
> 6. Detects pflip_status == AMDGPU_FLIP_SUBMITTED and assumes the
>    pageflip has been completed/will complete in this vblank and
>    sends out pageflip completion event to userspace and resets
>    pflip_status = AMDGPU_FLIP_NONE.
>
> => Flip completion event sent out one vblank too early.
>
> This behaviour has been observed during my testing with measurement
> hardware a couple of time.
>
> The commit message says that the extra flip event code was added to
> dm_dcn_crtc_high_irq() to prevent missing to send out pageflip events
> in case the pflip irq doesn't fire, because the "DCH HUBP" component
> is clock gated and doesn't fire pflip irqs in that state. Also that
> this clock gating may happen if no planes are active. According to
> Nicholas, the clock gating can also happen if psr is active, and the
> gating is controlled independently by the hardware, so difficult to
> detect if and when the completion code in above commit is needed.
>
> This patch tries the following solution: It only executes the extra pflip
> completion code in dm_dcn_crtc_high_irq() iff the hardware reports
> that there aren't any surface updated pending in the double-buffered
> surface scanout address registers. Otherwise it leaves pflip completion
> to the pflip irq handler, for a more race-free experience.
>
> This would only guard against the order of events mentioned above.
> If Step 5 (VSTARTUP trigger) happens before step 4 then this won't help
> at all, because 1-3 + 5 might happen even without the hw being programmed
> at all, ie. no surface update pending because none yet programmed into hw.
>
> Therefore this patch also changes locking in amdgpu_dm_commit_planes(),
> so that prepare_flip_isr() and dc_commit_updates_for_stream() are done
> under event_lock protection within the same critical section.
>
> v2: Take Nicholas comments into account, try a different solution.
>
> Lightly tested on Polaris (locking) and Raven (the whole DCN stuff).
> Seems to work without causing obvious new trouble.

Nick, any comments on this?  Can we get this committed or do you think
it needs additional rework?

Thanks,

Alex

>
> Fixes: 16f17eda8bad ("drm/amd/display: Send vblank and user events at vsartup for DCN")
> Signed-off-by: Mario Kleiner <[e-mail]>
> ---
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 80 ++++++++++++++++---
>  1 file changed, 67 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index d7df1a85e72f..aa4e941b276f 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -287,6 +287,28 @@ static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
>                dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
>  }
>
> +/**
> + * dm_crtc_is_flip_pending() - Is a pageflip pending on this crtc?
> + *
> + * Returns true if any plane on the crtc has a flip pending, false otherwise.
> + */
> +static bool dm_crtc_is_flip_pending(struct dm_crtc_state *acrtc_state)
> +{
> +       struct dc_stream_status *status = dc_stream_get_status(acrtc_state->stream);
> +       const struct dc_plane_status *plane_status;
> +       int i;
> +       bool pending = false;
> +
> +       for (i = 0; i < status->plane_count; i++) {
> +               plane_status = dc_plane_get_status(status->plane_states[i]);
> +               pending |= plane_status->is_flip_pending;
> +               DRM_DEBUG_DRIVER("plane:%d, flip_pending=%d\n",
> +                                i, plane_status->is_flip_pending);
> +       }
> +
> +       return pending;
> +}
> +
>  /**
>   * dm_pflip_high_irq() - Handle pageflip interrupt
>   * @interrupt_params: ignored
> @@ -435,6 +457,11 @@ static void dm_vupdate_high_irq(void *interrupt_params)
>                                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
>                         }
>                 }
> +
> +               if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
> +                       DRM_DEBUG_DRIVER("%s:crtc:%d, flip_pending=%d\n", __func__,
> +                                           acrtc->crtc_id, dm_crtc_is_flip_pending(acrtc_state));
> +               }
>         }
>  }
>
> @@ -489,6 +516,11 @@ static void dm_crtc_high_irq(void *interrupt_params)
>                                 &acrtc_state->vrr_params.adjust);
>                         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
>                 }
> +
> +               if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
> +                       DRM_DEBUG_DRIVER("%s:crtc:%d, flip_pending=%d\n", __func__,
> +                                        acrtc->crtc_id, dm_crtc_is_flip_pending(acrtc_state));
> +               }
>         }
>  }
>
> @@ -543,13 +575,29 @@ static void dm_dcn_crtc_high_irq(void *interrupt_params)
>                         &acrtc_state->vrr_params.adjust);
>         }
>
> -       if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
> +       /*
> +        * If there aren't any active_planes, or PSR is active, then DCH HUBP
> +        * may be clock-gated. In that state, pageflip completion interrupts
> +        * won't fire and pageflip completion events won't get delivered.
> +        *
> +        * Prevent this by sending pending pageflip events from here if a flip
> +        * has been submitted, but is no longer pending in hw, ie. has already
> +        * completed.
> +        *
> +        * If the flip is still pending in hw, then use dm_pflip_high_irq()
> +        * instead, handling completion as usual by pflip irq.
> +        */
> +       if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
> +           !dm_crtc_is_flip_pending(acrtc_state)) {
>                 if (acrtc->event) {
>                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
>                         acrtc->event = NULL;
>                         drm_crtc_vblank_put(&acrtc->base);
>                 }
>                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
> +
> +               DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_NONE\n",
> +                                acrtc->crtc_id);
>         }
>
>         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
> @@ -6325,7 +6373,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
>                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
>         int planes_count = 0, vpos, hpos;
>         long r;
> -       unsigned long flags;
> +       unsigned long flags = 0;
>         struct amdgpu_bo *abo;
>         uint64_t tiling_flags;
>         uint32_t target_vblank, last_flip_vblank;
> @@ -6513,17 +6561,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
>                         usleep_range(1000, 1100);
>                 }
>
> -               if (acrtc_attach->base.state->event) {
> -                       drm_crtc_vblank_get(pcrtc);
> -
> -                       spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
> -
> -                       WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
> -                       prepare_flip_isr(acrtc_attach);
> -
> -                       spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
> -               }
> -
>                 if (acrtc_state->stream) {
>                         if (acrtc_state->freesync_vrr_info_changed)
>                                 bundle->stream_update.vrr_infopacket =
> @@ -6575,6 +6612,15 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
>                                 acrtc_state->stream->link->psr_allow_active)
>                         amdgpu_dm_psr_disable(acrtc_state->stream);
>
> +               if (pflip_present && acrtc_attach->base.state->event) {
> +                       drm_crtc_vblank_get(pcrtc);
> +
> +                       spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
> +
> +                       WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
> +                       prepare_flip_isr(acrtc_attach);
> +               }
> +
>                 dc_commit_updates_for_stream(dm->dc,
>                                                      bundle->surface_updates,
>                                                      planes_count,
> @@ -6582,6 +6628,14 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
>                                                      &bundle->stream_update,
>                                                      dc_state);
>
> +               /*
> +                * Must event_lock protect prepare_flip_isr() above and
> +                * dc_commit_updates_for_stream within same critical section,
> +                * or pageflip completion will suffer bad races on DCN.
> +                */
> +               if (pflip_present && acrtc_attach->pflip_status == AMDGPU_FLIP_SUBMITTED)
> +                       spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
> +
>                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
>                                                 acrtc_state->stream->psr_version &&
>                                                 !acrtc_state->stream->link->psr_feature_enabled)
> --
> 2.20.1
>
> _______________________________________________
> amd-gfx mailing list
> [e-mail]
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Kazlauskas, Nicholas March 13, 2020, 12:35 p.m. UTC | #2

On 2020-03-12 10:32 a.m., Alex Deucher wrote:
> On Thu, Mar 5, 2020 at 4:21 PM Mario Kleiner <[e-mail]> wrote:
>>
>> Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
>> events at vsartup for DCN")' introduces a new way of pageflip
>> completion handling for DCN, and some trouble.
>>
>> The current implementation introduces a race condition, which
>> can cause pageflip completion events to be sent out one vblank
>> too early, thereby confusing userspace and causing flicker:
>>
>> prepare_flip_isr():
>>
>> 1. Pageflip programming takes the ddev->event_lock.
>> 2. Sets acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED
>> 3. Releases ddev->event_lock.
>>
>> --> Deadline for surface address regs double-buffering passes on
>>      target pipe.
>>
>> 4. dc_commit_updates_for_stream() MMIO programs the new pageflip
>>     into hw, but too late for current vblank.
>>
>> => pflip_status == AMDGPU_FLIP_SUBMITTED, but flip won't complete
>>     in current vblank due to missing the double-buffering deadline
>>     by a tiny bit.
>>
>> 5. VSTARTUP trigger point in vblank is reached, VSTARTUP irq fires,
>>     dm_dcn_crtc_high_irq() gets called.
>>
>> 6. Detects pflip_status == AMDGPU_FLIP_SUBMITTED and assumes the
>>     pageflip has been completed/will complete in this vblank and
>>     sends out pageflip completion event to userspace and resets
>>     pflip_status = AMDGPU_FLIP_NONE.
>>
>> => Flip completion event sent out one vblank too early.
>>
>> This behaviour has been observed during my testing with measurement
>> hardware a couple of time.
>>
>> The commit message says that the extra flip event code was added to
>> dm_dcn_crtc_high_irq() to prevent missing to send out pageflip events
>> in case the pflip irq doesn't fire, because the "DCH HUBP" component
>> is clock gated and doesn't fire pflip irqs in that state. Also that
>> this clock gating may happen if no planes are active. According to
>> Nicholas, the clock gating can also happen if psr is active, and the
>> gating is controlled independently by the hardware, so difficult to
>> detect if and when the completion code in above commit is needed.
>>
>> This patch tries the following solution: It only executes the extra pflip
>> completion code in dm_dcn_crtc_high_irq() iff the hardware reports
>> that there aren't any surface updated pending in the double-buffered
>> surface scanout address registers. Otherwise it leaves pflip completion
>> to the pflip irq handler, for a more race-free experience.
>>
>> This would only guard against the order of events mentioned above.
>> If Step 5 (VSTARTUP trigger) happens before step 4 then this won't help
>> at all, because 1-3 + 5 might happen even without the hw being programmed
>> at all, ie. no surface update pending because none yet programmed into hw.
>>
>> Therefore this patch also changes locking in amdgpu_dm_commit_planes(),
>> so that prepare_flip_isr() and dc_commit_updates_for_stream() are done
>> under event_lock protection within the same critical section.
>>
>> v2: Take Nicholas comments into account, try a different solution.
>>
>> Lightly tested on Polaris (locking) and Raven (the whole DCN stuff).
>> Seems to work without causing obvious new trouble.
> 
> Nick, any comments on this?  Can we get this committed or do you think
> it needs additional rework?
> 
> Thanks,
> 
> Alex

Hi Alex, Mario,

This might be a little strange, but if we want to get this in as a fix 
for regressions caused by the original vblank and user events at 
vstartup patch then I'm actually going to give my reviewed by on the 
*v1* of this patch (but not this v2):

Reviewed-by: Nicholas Kazlauskas <[e-mail]>

You can feel free to apply that one.

Reason 1: After having thought about it some more I don't think we 
enable anything today that has hubp powered down at the same time we 
expect to be waiting for a flip - eg. DMCU powering down HUBP during PSR 
entry. Static screen interrupt should happen after that flip finishes I 
think.

The CRTC can still be powered on with zero planes, and I don't think any 
userspace explicitly asks for vblank events in this case but it doesn't 
hurt to have the check.

Reason 2: This new patch will need much more thorough testing from side 
to fully understand the consequences of locking the entire DC commit 
sequence. For just a page flip that sounds fine, but for anything more 
than (eg. full updates, modesets, etc) I don't think we want to be 
disabling interrupts for potentially many milliseconds.

Maybe we could just use a lock-free queue here for the events. It's 
single producer/single consumer per CRTC.

Regards,
Nicholas Kazlauskas

> 
>>
>> Fixes: 16f17eda8bad ("drm/amd/display: Send vblank and user events at vsartup for DCN")
>> Signed-off-by: Mario Kleiner <[e-mail]>
>> ---
>>   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 80 ++++++++++++++++---
>>   1 file changed, 67 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index d7df1a85e72f..aa4e941b276f 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -287,6 +287,28 @@ static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
>>                 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
>>   }
>>
>> +/**
>> + * dm_crtc_is_flip_pending() - Is a pageflip pending on this crtc?
>> + *
>> + * Returns true if any plane on the crtc has a flip pending, false otherwise.
>> + */
>> +static bool dm_crtc_is_flip_pending(struct dm_crtc_state *acrtc_state)
>> +{
>> +       struct dc_stream_status *status = dc_stream_get_status(acrtc_state->stream);
>> +       const struct dc_plane_status *plane_status;
>> +       int i;
>> +       bool pending = false;
>> +
>> +       for (i = 0; i < status->plane_count; i++) {
>> +               plane_status = dc_plane_get_status(status->plane_states[i]);
>> +               pending |= plane_status->is_flip_pending;
>> +               DRM_DEBUG_DRIVER("plane:%d, flip_pending=%d\n",
>> +                                i, plane_status->is_flip_pending);
>> +       }
>> +
>> +       return pending;
>> +}
>> +
>>   /**
>>    * dm_pflip_high_irq() - Handle pageflip interrupt
>>    * @interrupt_params: ignored
>> @@ -435,6 +457,11 @@ static void dm_vupdate_high_irq(void *interrupt_params)
>>                                  spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
>>                          }
>>                  }
>> +
>> +               if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
>> +                       DRM_DEBUG_DRIVER("%s:crtc:%d, flip_pending=%d\n", __func__,
>> +                                           acrtc->crtc_id, dm_crtc_is_flip_pending(acrtc_state));
>> +               }
>>          }
>>   }
>>
>> @@ -489,6 +516,11 @@ static void dm_crtc_high_irq(void *interrupt_params)
>>                                  &acrtc_state->vrr_params.adjust);
>>                          spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
>>                  }
>> +
>> +               if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
>> +                       DRM_DEBUG_DRIVER("%s:crtc:%d, flip_pending=%d\n", __func__,
>> +                                        acrtc->crtc_id, dm_crtc_is_flip_pending(acrtc_state));
>> +               }
>>          }
>>   }
>>
>> @@ -543,13 +575,29 @@ static void dm_dcn_crtc_high_irq(void *interrupt_params)
>>                          &acrtc_state->vrr_params.adjust);
>>          }
>>
>> -       if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
>> +       /*
>> +        * If there aren't any active_planes, or PSR is active, then DCH HUBP
>> +        * may be clock-gated. In that state, pageflip completion interrupts
>> +        * won't fire and pageflip completion events won't get delivered.
>> +        *
>> +        * Prevent this by sending pending pageflip events from here if a flip
>> +        * has been submitted, but is no longer pending in hw, ie. has already
>> +        * completed.
>> +        *
>> +        * If the flip is still pending in hw, then use dm_pflip_high_irq()
>> +        * instead, handling completion as usual by pflip irq.
>> +        */
>> +       if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
>> +           !dm_crtc_is_flip_pending(acrtc_state)) {
>>                  if (acrtc->event) {
>>                          drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
>>                          acrtc->event = NULL;
>>                          drm_crtc_vblank_put(&acrtc->base);
>>                  }
>>                  acrtc->pflip_status = AMDGPU_FLIP_NONE;
>> +
>> +               DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_NONE\n",
>> +                                acrtc->crtc_id);
>>          }
>>
>>          spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
>> @@ -6325,7 +6373,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
>>                          to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
>>          int planes_count = 0, vpos, hpos;
>>          long r;
>> -       unsigned long flags;
>> +       unsigned long flags = 0;
>>          struct amdgpu_bo *abo;
>>          uint64_t tiling_flags;
>>          uint32_t target_vblank, last_flip_vblank;
>> @@ -6513,17 +6561,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
>>                          usleep_range(1000, 1100);
>>                  }
>>
>> -               if (acrtc_attach->base.state->event) {
>> -                       drm_crtc_vblank_get(pcrtc);
>> -
>> -                       spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
>> -
>> -                       WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
>> -                       prepare_flip_isr(acrtc_attach);
>> -
>> -                       spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
>> -               }
>> -
>>                  if (acrtc_state->stream) {
>>                          if (acrtc_state->freesync_vrr_info_changed)
>>                                  bundle->stream_update.vrr_infopacket =
>> @@ -6575,6 +6612,15 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
>>                                  acrtc_state->stream->link->psr_allow_active)
>>                          amdgpu_dm_psr_disable(acrtc_state->stream);
>>
>> +               if (pflip_present && acrtc_attach->base.state->event) {
>> +                       drm_crtc_vblank_get(pcrtc);
>> +
>> +                       spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
>> +
>> +                       WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
>> +                       prepare_flip_isr(acrtc_attach);
>> +               }
>> +
>>                  dc_commit_updates_for_stream(dm->dc,
>>                                                       bundle->surface_updates,
>>                                                       planes_count,
>> @@ -6582,6 +6628,14 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
>>                                                       &bundle->stream_update,
>>                                                       dc_state);
>>
>> +               /*
>> +                * Must event_lock protect prepare_flip_isr() above and
>> +                * dc_commit_updates_for_stream within same critical section,
>> +                * or pageflip completion will suffer bad races on DCN.
>> +                */
>> +               if (pflip_present && acrtc_attach->pflip_status == AMDGPU_FLIP_SUBMITTED)
>> +                       spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
>> +
>>                  if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
>>                                                  acrtc_state->stream->psr_version &&
>>                                                  !acrtc_state->stream->link->psr_feature_enabled)
>> --
>> 2.20.1
>>
>> _______________________________________________
>> amd-gfx mailing list
>> [e-mail]
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Michel Dänzer March 13, 2020, 2:42 p.m. UTC | #3

On 2020-03-13 1:35 p.m., Kazlauskas, Nicholas wrote:
> On 2020-03-12 10:32 a.m., Alex Deucher wrote:
>> On Thu, Mar 5, 2020 at 4:21 PM Mario Kleiner
>> <[e-mail]> wrote:
>>>
>>> Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
>>> events at vsartup for DCN")' introduces a new way of pageflip
>>> completion handling for DCN, and some trouble.
>>>
>>> The current implementation introduces a race condition, which
>>> can cause pageflip completion events to be sent out one vblank
>>> too early, thereby confusing userspace and causing flicker:
>>>
>>> prepare_flip_isr():
>>>
>>> 1. Pageflip programming takes the ddev->event_lock.
>>> 2. Sets acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED
>>> 3. Releases ddev->event_lock.
>>>
>>> --> Deadline for surface address regs double-buffering passes on
>>>      target pipe.
>>>
>>> 4. dc_commit_updates_for_stream() MMIO programs the new pageflip
>>>     into hw, but too late for current vblank.
>>>
>>> => pflip_status == AMDGPU_FLIP_SUBMITTED, but flip won't complete
>>>     in current vblank due to missing the double-buffering deadline
>>>     by a tiny bit.
>>>
>>> 5. VSTARTUP trigger point in vblank is reached, VSTARTUP irq fires,
>>>     dm_dcn_crtc_high_irq() gets called.
>>>
>>> 6. Detects pflip_status == AMDGPU_FLIP_SUBMITTED and assumes the
>>>     pageflip has been completed/will complete in this vblank and
>>>     sends out pageflip completion event to userspace and resets
>>>     pflip_status = AMDGPU_FLIP_NONE.
>>>
>>> => Flip completion event sent out one vblank too early.
>>>
>>> This behaviour has been observed during my testing with measurement
>>> hardware a couple of time.
>>>
>>> The commit message says that the extra flip event code was added to
>>> dm_dcn_crtc_high_irq() to prevent missing to send out pageflip events
>>> in case the pflip irq doesn't fire, because the "DCH HUBP" component
>>> is clock gated and doesn't fire pflip irqs in that state. Also that
>>> this clock gating may happen if no planes are active. According to
>>> Nicholas, the clock gating can also happen if psr is active, and the
>>> gating is controlled independently by the hardware, so difficult to
>>> detect if and when the completion code in above commit is needed.
>>>
>>> This patch tries the following solution: It only executes the extra
>>> pflip
>>> completion code in dm_dcn_crtc_high_irq() iff the hardware reports
>>> that there aren't any surface updated pending in the double-buffered
>>> surface scanout address registers. Otherwise it leaves pflip completion
>>> to the pflip irq handler, for a more race-free experience.
>>>
>>> This would only guard against the order of events mentioned above.
>>> If Step 5 (VSTARTUP trigger) happens before step 4 then this won't help
>>> at all, because 1-3 + 5 might happen even without the hw being
>>> programmed
>>> at all, ie. no surface update pending because none yet programmed
>>> into hw.
>>>
>>> Therefore this patch also changes locking in amdgpu_dm_commit_planes(),
>>> so that prepare_flip_isr() and dc_commit_updates_for_stream() are done
>>> under event_lock protection within the same critical section.
>>>
>>> v2: Take Nicholas comments into account, try a different solution.
>>>
>>> Lightly tested on Polaris (locking) and Raven (the whole DCN stuff).
>>> Seems to work without causing obvious new trouble.
>>
>> Nick, any comments on this?  Can we get this committed or do you think
>> it needs additional rework?
>>
>> Thanks,
>>
>> Alex
> 
> Hi Alex, Mario,
> 
> This might be a little strange, but if we want to get this in as a fix
> for regressions caused by the original vblank and user events at
> vstartup patch then I'm actually going to give my reviewed by on the
> *v1* of this patch (but not this v2):
> 
> Reviewed-by: Nicholas Kazlauskas <[e-mail]>
> 
> You can feel free to apply that one.
> 
> Reason 1: After having thought about it some more I don't think we
> enable anything today that has hubp powered down at the same time we
> expect to be waiting for a flip - eg. DMCU powering down HUBP during PSR
> entry. Static screen interrupt should happen after that flip finishes I
> think.
> 
> The CRTC can still be powered on with zero planes, and I don't think any
> userspace explicitly asks for vblank events in this case but it doesn't
> hurt to have the check.
> 
> Reason 2: This new patch will need much more thorough testing from side
> to fully understand the consequences of locking the entire DC commit
> sequence. For just a page flip that sounds fine, but for anything more
> than (eg. full updates, modesets, etc) I don't think we want to be
> disabling interrupts for potentially many milliseconds.

Ah! I was wondering where the attached splat comes from, but I think
this explains it: With this patch amdgpu_dm_commit_planes keeps the
pcrtc->dev->event_lock spinlock locked while calling
dc_commit_updates_for_stream, which ends up calling
smu_set_display_count, which tries to lock a mutex.

Mario Kleiner March 13, 2020, 9:52 p.m. UTC | #4

On Fri, Mar 13, 2020 at 5:02 PM Michel Dänzer <[e-mail]> wrote:

> On 2020-03-13 1:35 p.m., Kazlauskas, Nicholas wrote:
> > On 2020-03-12 10:32 a.m., Alex Deucher wrote:
> >> On Thu, Mar 5, 2020 at 4:21 PM Mario Kleiner
> >> <[e-mail]> wrote:
> >>>
> >>> Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
> >>> events at vsartup for DCN")' introduces a new way of pageflip
> >>> completion handling for DCN, and some trouble.
> >>>
> >>> The current implementation introduces a race condition, which
> >>> can cause pageflip completion events to be sent out one vblank
> >>> too early, thereby confusing userspace and causing flicker:
> >>>
> >>> prepare_flip_isr():
> >>>
> >>> 1. Pageflip programming takes the ddev->event_lock.
> >>> 2. Sets acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED
> >>> 3. Releases ddev->event_lock.
> >>>
> >>> --> Deadline for surface address regs double-buffering passes on
> >>>      target pipe.
> >>>
> >>> 4. dc_commit_updates_for_stream() MMIO programs the new pageflip
> >>>     into hw, but too late for current vblank.
> >>>
> >>> => pflip_status == AMDGPU_FLIP_SUBMITTED, but flip won't complete
> >>>     in current vblank due to missing the double-buffering deadline
> >>>     by a tiny bit.
> >>>
> >>> 5. VSTARTUP trigger point in vblank is reached, VSTARTUP irq fires,
> >>>     dm_dcn_crtc_high_irq() gets called.
> >>>
> >>> 6. Detects pflip_status == AMDGPU_FLIP_SUBMITTED and assumes the
> >>>     pageflip has been completed/will complete in this vblank and
> >>>     sends out pageflip completion event to userspace and resets
> >>>     pflip_status = AMDGPU_FLIP_NONE.
> >>>
> >>> => Flip completion event sent out one vblank too early.
> >>>
> >>> This behaviour has been observed during my testing with measurement
> >>> hardware a couple of time.
> >>>
> >>> The commit message says that the extra flip event code was added to
> >>> dm_dcn_crtc_high_irq() to prevent missing to send out pageflip events
> >>> in case the pflip irq doesn't fire, because the "DCH HUBP" component
> >>> is clock gated and doesn't fire pflip irqs in that state. Also that
> >>> this clock gating may happen if no planes are active. According to
> >>> Nicholas, the clock gating can also happen if psr is active, and the
> >>> gating is controlled independently by the hardware, so difficult to
> >>> detect if and when the completion code in above commit is needed.
> >>>
> >>> This patch tries the following solution: It only executes the extra
> >>> pflip
> >>> completion code in dm_dcn_crtc_high_irq() iff the hardware reports
> >>> that there aren't any surface updated pending in the double-buffered
> >>> surface scanout address registers. Otherwise it leaves pflip completion
> >>> to the pflip irq handler, for a more race-free experience.
> >>>
> >>> This would only guard against the order of events mentioned above.
> >>> If Step 5 (VSTARTUP trigger) happens before step 4 then this won't help
> >>> at all, because 1-3 + 5 might happen even without the hw being
> >>> programmed
> >>> at all, ie. no surface update pending because none yet programmed
> >>> into hw.
> >>>
> >>> Therefore this patch also changes locking in amdgpu_dm_commit_planes(),
> >>> so that prepare_flip_isr() and dc_commit_updates_for_stream() are done
> >>> under event_lock protection within the same critical section.
> >>>
> >>> v2: Take Nicholas comments into account, try a different solution.
> >>>
> >>> Lightly tested on Polaris (locking) and Raven (the whole DCN stuff).
> >>> Seems to work without causing obvious new trouble.
> >>
> >> Nick, any comments on this?  Can we get this committed or do you think
> >> it needs additional rework?
> >>
> >> Thanks,
> >>
> >> Alex
> >
> > Hi Alex, Mario,
> >
> > This might be a little strange, but if we want to get this in as a fix
> > for regressions caused by the original vblank and user events at
> > vstartup patch then I'm actually going to give my reviewed by on the
> > *v1* of this patch (but not this v2):
> >
> > Reviewed-by: Nicholas Kazlauskas <[e-mail]>
> >
> > You can feel free to apply that one.
> >
> > Reason 1: After having thought about it some more I don't think we
> > enable anything today that has hubp powered down at the same time we
> > expect to be waiting for a flip - eg. DMCU powering down HUBP during PSR
> > entry. Static screen interrupt should happen after that flip finishes I
> > think.
> >
> > The CRTC can still be powered on with zero planes, and I don't think any
> > userspace explicitly asks for vblank events in this case but it doesn't
> > hurt to have the check.
> >
>

Ok, so the original commit that causes the races currently solves a
non-existing - but potential future - problem?

I guess then my v1 patch makes sense for the moment and fixes the immediate
problem for Linux 5.6-rc.

Maybe there's a way to ask the hw if hubp is clock-gated and so if that
code needs to run or not in the future?

As mentioned before, it would be helpful at least for me to get a better
overview about which hw events happen when in vblank, which irq's fire in
response etc., how this relates to things like power management actions,
psr, vrr / drr, etc. A lot has changed in the hw during the last 10 years,
and my guideline are still the public pdf files with the DCE register specs
for DCE-1'ish hw from sometime around the year 2007.

> Reason 2: This new patch will need much more thorough testing from side
> > to fully understand the consequences of locking the entire DC commit
> > sequence. For just a page flip that sounds fine, but for anything more
> > than (eg. full updates, modesets, etc) I don't think we want to be
> > disabling interrupts for potentially many milliseconds.
>
> Ah! I was wondering where the attached splat comes from, but I think
> this explains it: With this patch amdgpu_dm_commit_planes keeps the
> pcrtc->dev->event_lock spinlock locked while calling
> dc_commit_updates_for_stream, which ends up calling
> smu_set_display_count, which tries to lock a mutex.
>
>
Yep, sorry about that. My most modern machine has Raven Ridge / DCN1, and
that function only gets called on Navi /DCN2 afaics. All my testing is
limited to Polaris / DCE11 and Raven DCN1, my most modern hw atm.

thanks,
-mario

Matt Coffin April 14, 2020, 11:32 p.m. UTC | #5

Hey everyone,

This patch broke variable refresh rate in games (all that I've tried so
far... Project CARS 2, DiRT Rally 2.0, Assetto Corsa Competizione) as
well as a simple freesync tester application.

FreeSync tester I've been using: https://github.com/Nixola/VRRTest

I'm not at all familiar with the page flipping code, so it would take me
a long time to find the *right* way to fix it, but does someone else see
why it would do that?

The symptom is that the refresh rate of the display constantly bounces
between the two ends of the FreeSync range (for me 40 -> 144), and the
game stutters like a madman.

Any help on where to start, ideas on how to fix it (other than just
revert this commit, which I've done in the interim), or alternative
patches would be appreciated.

Thanks in advance for the work/help,
Matt

On 3/13/20 8:42 AM, Michel Dänzer wrote:
> On 2020-03-13 1:35 p.m., Kazlauskas, Nicholas wrote:
>> On 2020-03-12 10:32 a.m., Alex Deucher wrote:
>>> On Thu, Mar 5, 2020 at 4:21 PM Mario Kleiner
>>> <[e-mail]> wrote:
>>>>
>>>> Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
>>>> events at vsartup for DCN")' introduces a new way of pageflip
>>>> completion handling for DCN, and some trouble.
>>>>
>>>> The current implementation introduces a race condition, which
>>>> can cause pageflip completion events to be sent out one vblank
>>>> too early, thereby confusing userspace and causing flicker:
>>>>
>>>> prepare_flip_isr():
>>>>
>>>> 1. Pageflip programming takes the ddev->event_lock.
>>>> 2. Sets acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED
>>>> 3. Releases ddev->event_lock.
>>>>
>>>> --> Deadline for surface address regs double-buffering passes on
>>>>      target pipe.
>>>>
>>>> 4. dc_commit_updates_for_stream() MMIO programs the new pageflip
>>>>     into hw, but too late for current vblank.
>>>>
>>>> => pflip_status == AMDGPU_FLIP_SUBMITTED, but flip won't complete
>>>>     in current vblank due to missing the double-buffering deadline
>>>>     by a tiny bit.
>>>>
>>>> 5. VSTARTUP trigger point in vblank is reached, VSTARTUP irq fires,
>>>>     dm_dcn_crtc_high_irq() gets called.
>>>>
>>>> 6. Detects pflip_status == AMDGPU_FLIP_SUBMITTED and assumes the
>>>>     pageflip has been completed/will complete in this vblank and
>>>>     sends out pageflip completion event to userspace and resets
>>>>     pflip_status = AMDGPU_FLIP_NONE.
>>>>
>>>> => Flip completion event sent out one vblank too early.
>>>>
>>>> This behaviour has been observed during my testing with measurement
>>>> hardware a couple of time.
>>>>
>>>> The commit message says that the extra flip event code was added to
>>>> dm_dcn_crtc_high_irq() to prevent missing to send out pageflip events
>>>> in case the pflip irq doesn't fire, because the "DCH HUBP" component
>>>> is clock gated and doesn't fire pflip irqs in that state. Also that
>>>> this clock gating may happen if no planes are active. According to
>>>> Nicholas, the clock gating can also happen if psr is active, and the
>>>> gating is controlled independently by the hardware, so difficult to
>>>> detect if and when the completion code in above commit is needed.
>>>>
>>>> This patch tries the following solution: It only executes the extra
>>>> pflip
>>>> completion code in dm_dcn_crtc_high_irq() iff the hardware reports
>>>> that there aren't any surface updated pending in the double-buffered
>>>> surface scanout address registers. Otherwise it leaves pflip completion
>>>> to the pflip irq handler, for a more race-free experience.
>>>>
>>>> This would only guard against the order of events mentioned above.
>>>> If Step 5 (VSTARTUP trigger) happens before step 4 then this won't help
>>>> at all, because 1-3 + 5 might happen even without the hw being
>>>> programmed
>>>> at all, ie. no surface update pending because none yet programmed
>>>> into hw.
>>>>
>>>> Therefore this patch also changes locking in amdgpu_dm_commit_planes(),
>>>> so that prepare_flip_isr() and dc_commit_updates_for_stream() are done
>>>> under event_lock protection within the same critical section.
>>>>
>>>> v2: Take Nicholas comments into account, try a different solution.
>>>>
>>>> Lightly tested on Polaris (locking) and Raven (the whole DCN stuff).
>>>> Seems to work without causing obvious new trouble.
>>>
>>> Nick, any comments on this?  Can we get this committed or do you think
>>> it needs additional rework?
>>>
>>> Thanks,
>>>
>>> Alex
>>
>> Hi Alex, Mario,
>>
>> This might be a little strange, but if we want to get this in as a fix
>> for regressions caused by the original vblank and user events at
>> vstartup patch then I'm actually going to give my reviewed by on the
>> *v1* of this patch (but not this v2):
>>
>> Reviewed-by: Nicholas Kazlauskas <[e-mail]>
>>
>> You can feel free to apply that one.
>>
>> Reason 1: After having thought about it some more I don't think we
>> enable anything today that has hubp powered down at the same time we
>> expect to be waiting for a flip - eg. DMCU powering down HUBP during PSR
>> entry. Static screen interrupt should happen after that flip finishes I
>> think.
>>
>> The CRTC can still be powered on with zero planes, and I don't think any
>> userspace explicitly asks for vblank events in this case but it doesn't
>> hurt to have the check.
>>
>> Reason 2: This new patch will need much more thorough testing from side
>> to fully understand the consequences of locking the entire DC commit
>> sequence. For just a page flip that sounds fine, but for anything more
>> than (eg. full updates, modesets, etc) I don't think we want to be
>> disabling interrupts for potentially many milliseconds.
> 
> Ah! I was wondering where the attached splat comes from, but I think
> this explains it: With this patch amdgpu_dm_commit_planes keeps the
> pcrtc->dev->event_lock spinlock locked while calling
> dc_commit_updates_for_stream, which ends up calling
> smu_set_display_count, which tries to lock a mutex.
> 
> 
> 
> _______________________________________________
> amd-gfx mailing list
> [e-mail]
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>

Matt Coffin May 4, 2020, 5:35 p.m. UTC | #6

Hey guys,

This is still an issue for me, and I'm still having to run a patch to
revert this as of 5.7-rc4. To avoid breaking a lot of people's Navi
setups in 5.7, is there any news on this? Has anyone else at the very
least been able to reproduce the problem?

It happens for me in every single program that mesa allows to utilize
variable refresh rates, and reverting it "fixes" the issue.

Cheers, and sorry for the extra email, just making sure this is still on
someone's radar,
Matt

On 4/14/20 5:32 PM, Matt Coffin wrote:
> Hey everyone,
> 
> This patch broke variable refresh rate in games (all that I've tried so
> far... Project CARS 2, DiRT Rally 2.0, Assetto Corsa Competizione) as
> well as a simple freesync tester application.
> 
> FreeSync tester I've been using: https://github.com/Nixola/VRRTest
> 
> I'm not at all familiar with the page flipping code, so it would take me
> a long time to find the *right* way to fix it, but does someone else see
> why it would do that?
> 
> The symptom is that the refresh rate of the display constantly bounces
> between the two ends of the FreeSync range (for me 40 -> 144), and the
> game stutters like a madman.
> 
> Any help on where to start, ideas on how to fix it (other than just
> revert this commit, which I've done in the interim), or alternative
> patches would be appreciated.
> 
> Thanks in advance for the work/help,
> Matt
> 
> On 3/13/20 8:42 AM, Michel Dänzer wrote:
>> On 2020-03-13 1:35 p.m., Kazlauskas, Nicholas wrote:
>>> On 2020-03-12 10:32 a.m., Alex Deucher wrote:
>>>> On Thu, Mar 5, 2020 at 4:21 PM Mario Kleiner
>>>> <[e-mail]> wrote:
>>>>>
>>>>> Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
>>>>> events at vsartup for DCN")' introduces a new way of pageflip
>>>>> completion handling for DCN, and some trouble.
>>>>>
>>>>> The current implementation introduces a race condition, which
>>>>> can cause pageflip completion events to be sent out one vblank
>>>>> too early, thereby confusing userspace and causing flicker:
>>>>>
>>>>> prepare_flip_isr():
>>>>>
>>>>> 1. Pageflip programming takes the ddev->event_lock.
>>>>> 2. Sets acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED
>>>>> 3. Releases ddev->event_lock.
>>>>>
>>>>> --> Deadline for surface address regs double-buffering passes on
>>>>>      target pipe.
>>>>>
>>>>> 4. dc_commit_updates_for_stream() MMIO programs the new pageflip
>>>>>     into hw, but too late for current vblank.
>>>>>
>>>>> => pflip_status == AMDGPU_FLIP_SUBMITTED, but flip won't complete
>>>>>     in current vblank due to missing the double-buffering deadline
>>>>>     by a tiny bit.
>>>>>
>>>>> 5. VSTARTUP trigger point in vblank is reached, VSTARTUP irq fires,
>>>>>     dm_dcn_crtc_high_irq() gets called.
>>>>>
>>>>> 6. Detects pflip_status == AMDGPU_FLIP_SUBMITTED and assumes the
>>>>>     pageflip has been completed/will complete in this vblank and
>>>>>     sends out pageflip completion event to userspace and resets
>>>>>     pflip_status = AMDGPU_FLIP_NONE.
>>>>>
>>>>> => Flip completion event sent out one vblank too early.
>>>>>
>>>>> This behaviour has been observed during my testing with measurement
>>>>> hardware a couple of time.
>>>>>
>>>>> The commit message says that the extra flip event code was added to
>>>>> dm_dcn_crtc_high_irq() to prevent missing to send out pageflip events
>>>>> in case the pflip irq doesn't fire, because the "DCH HUBP" component
>>>>> is clock gated and doesn't fire pflip irqs in that state. Also that
>>>>> this clock gating may happen if no planes are active. According to
>>>>> Nicholas, the clock gating can also happen if psr is active, and the
>>>>> gating is controlled independently by the hardware, so difficult to
>>>>> detect if and when the completion code in above commit is needed.
>>>>>
>>>>> This patch tries the following solution: It only executes the extra
>>>>> pflip
>>>>> completion code in dm_dcn_crtc_high_irq() iff the hardware reports
>>>>> that there aren't any surface updated pending in the double-buffered
>>>>> surface scanout address registers. Otherwise it leaves pflip completion
>>>>> to the pflip irq handler, for a more race-free experience.
>>>>>
>>>>> This would only guard against the order of events mentioned above.
>>>>> If Step 5 (VSTARTUP trigger) happens before step 4 then this won't help
>>>>> at all, because 1-3 + 5 might happen even without the hw being
>>>>> programmed
>>>>> at all, ie. no surface update pending because none yet programmed
>>>>> into hw.
>>>>>
>>>>> Therefore this patch also changes locking in amdgpu_dm_commit_planes(),
>>>>> so that prepare_flip_isr() and dc_commit_updates_for_stream() are done
>>>>> under event_lock protection within the same critical section.
>>>>>
>>>>> v2: Take Nicholas comments into account, try a different solution.
>>>>>
>>>>> Lightly tested on Polaris (locking) and Raven (the whole DCN stuff).
>>>>> Seems to work without causing obvious new trouble.
>>>>
>>>> Nick, any comments on this?  Can we get this committed or do you think
>>>> it needs additional rework?
>>>>
>>>> Thanks,
>>>>
>>>> Alex
>>>
>>> Hi Alex, Mario,
>>>
>>> This might be a little strange, but if we want to get this in as a fix
>>> for regressions caused by the original vblank and user events at
>>> vstartup patch then I'm actually going to give my reviewed by on the
>>> *v1* of this patch (but not this v2):
>>>
>>> Reviewed-by: Nicholas Kazlauskas <[e-mail]>
>>>
>>> You can feel free to apply that one.
>>>
>>> Reason 1: After having thought about it some more I don't think we
>>> enable anything today that has hubp powered down at the same time we
>>> expect to be waiting for a flip - eg. DMCU powering down HUBP during PSR
>>> entry. Static screen interrupt should happen after that flip finishes I
>>> think.
>>>
>>> The CRTC can still be powered on with zero planes, and I don't think any
>>> userspace explicitly asks for vblank events in this case but it doesn't
>>> hurt to have the check.
>>>
>>> Reason 2: This new patch will need much more thorough testing from side
>>> to fully understand the consequences of locking the entire DC commit
>>> sequence. For just a page flip that sounds fine, but for anything more
>>> than (eg. full updates, modesets, etc) I don't think we want to be
>>> disabling interrupts for potentially many milliseconds.
>>
>> Ah! I was wondering where the attached splat comes from, but I think
>> this explains it: With this patch amdgpu_dm_commit_planes keeps the
>> pcrtc->dev->event_lock spinlock locked while calling
>> dc_commit_updates_for_stream, which ends up calling
>> smu_set_display_count, which tries to lock a mutex.
>>
>>
>>
>> _______________________________________________
>> amd-gfx mailing list
>> [e-mail]
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>

Alex Deucher May 5, 2020, 5:03 p.m. UTC | #7

Mario or Nick any thoughts?

Alex

On Mon, May 4, 2020 at 1:35 PM Matt Coffin <[e-mail]> wrote:
>
> Hey guys,
>
> This is still an issue for me, and I'm still having to run a patch to
> revert this as of 5.7-rc4. To avoid breaking a lot of people's Navi
> setups in 5.7, is there any news on this? Has anyone else at the very
> least been able to reproduce the problem?
>
> It happens for me in every single program that mesa allows to utilize
> variable refresh rates, and reverting it "fixes" the issue.
>
> Cheers, and sorry for the extra email, just making sure this is still on
> someone's radar,
> Matt
>
> On 4/14/20 5:32 PM, Matt Coffin wrote:
> > Hey everyone,
> >
> > This patch broke variable refresh rate in games (all that I've tried so
> > far... Project CARS 2, DiRT Rally 2.0, Assetto Corsa Competizione) as
> > well as a simple freesync tester application.
> >
> > FreeSync tester I've been using: https://github.com/Nixola/VRRTest
> >
> > I'm not at all familiar with the page flipping code, so it would take me
> > a long time to find the *right* way to fix it, but does someone else see
> > why it would do that?
> >
> > The symptom is that the refresh rate of the display constantly bounces
> > between the two ends of the FreeSync range (for me 40 -> 144), and the
> > game stutters like a madman.
> >
> > Any help on where to start, ideas on how to fix it (other than just
> > revert this commit, which I've done in the interim), or alternative
> > patches would be appreciated.
> >
> > Thanks in advance for the work/help,
> > Matt
> >
> > On 3/13/20 8:42 AM, Michel Dänzer wrote:
> >> On 2020-03-13 1:35 p.m., Kazlauskas, Nicholas wrote:
> >>> On 2020-03-12 10:32 a.m., Alex Deucher wrote:
> >>>> On Thu, Mar 5, 2020 at 4:21 PM Mario Kleiner
> >>>> <[e-mail]> wrote:
> >>>>>
> >>>>> Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
> >>>>> events at vsartup for DCN")' introduces a new way of pageflip
> >>>>> completion handling for DCN, and some trouble.
> >>>>>
> >>>>> The current implementation introduces a race condition, which
> >>>>> can cause pageflip completion events to be sent out one vblank
> >>>>> too early, thereby confusing userspace and causing flicker:
> >>>>>
> >>>>> prepare_flip_isr():
> >>>>>
> >>>>> 1. Pageflip programming takes the ddev->event_lock.
> >>>>> 2. Sets acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED
> >>>>> 3. Releases ddev->event_lock.
> >>>>>
> >>>>> --> Deadline for surface address regs double-buffering passes on
> >>>>>      target pipe.
> >>>>>
> >>>>> 4. dc_commit_updates_for_stream() MMIO programs the new pageflip
> >>>>>     into hw, but too late for current vblank.
> >>>>>
> >>>>> => pflip_status == AMDGPU_FLIP_SUBMITTED, but flip won't complete
> >>>>>     in current vblank due to missing the double-buffering deadline
> >>>>>     by a tiny bit.
> >>>>>
> >>>>> 5. VSTARTUP trigger point in vblank is reached, VSTARTUP irq fires,
> >>>>>     dm_dcn_crtc_high_irq() gets called.
> >>>>>
> >>>>> 6. Detects pflip_status == AMDGPU_FLIP_SUBMITTED and assumes the
> >>>>>     pageflip has been completed/will complete in this vblank and
> >>>>>     sends out pageflip completion event to userspace and resets
> >>>>>     pflip_status = AMDGPU_FLIP_NONE.
> >>>>>
> >>>>> => Flip completion event sent out one vblank too early.
> >>>>>
> >>>>> This behaviour has been observed during my testing with measurement
> >>>>> hardware a couple of time.
> >>>>>
> >>>>> The commit message says that the extra flip event code was added to
> >>>>> dm_dcn_crtc_high_irq() to prevent missing to send out pageflip events
> >>>>> in case the pflip irq doesn't fire, because the "DCH HUBP" component
> >>>>> is clock gated and doesn't fire pflip irqs in that state. Also that
> >>>>> this clock gating may happen if no planes are active. According to
> >>>>> Nicholas, the clock gating can also happen if psr is active, and the
> >>>>> gating is controlled independently by the hardware, so difficult to
> >>>>> detect if and when the completion code in above commit is needed.
> >>>>>
> >>>>> This patch tries the following solution: It only executes the extra
> >>>>> pflip
> >>>>> completion code in dm_dcn_crtc_high_irq() iff the hardware reports
> >>>>> that there aren't any surface updated pending in the double-buffered
> >>>>> surface scanout address registers. Otherwise it leaves pflip completion
> >>>>> to the pflip irq handler, for a more race-free experience.
> >>>>>
> >>>>> This would only guard against the order of events mentioned above.
> >>>>> If Step 5 (VSTARTUP trigger) happens before step 4 then this won't help
> >>>>> at all, because 1-3 + 5 might happen even without the hw being
> >>>>> programmed
> >>>>> at all, ie. no surface update pending because none yet programmed
> >>>>> into hw.
> >>>>>
> >>>>> Therefore this patch also changes locking in amdgpu_dm_commit_planes(),
> >>>>> so that prepare_flip_isr() and dc_commit_updates_for_stream() are done
> >>>>> under event_lock protection within the same critical section.
> >>>>>
> >>>>> v2: Take Nicholas comments into account, try a different solution.
> >>>>>
> >>>>> Lightly tested on Polaris (locking) and Raven (the whole DCN stuff).
> >>>>> Seems to work without causing obvious new trouble.
> >>>>
> >>>> Nick, any comments on this?  Can we get this committed or do you think
> >>>> it needs additional rework?
> >>>>
> >>>> Thanks,
> >>>>
> >>>> Alex
> >>>
> >>> Hi Alex, Mario,
> >>>
> >>> This might be a little strange, but if we want to get this in as a fix
> >>> for regressions caused by the original vblank and user events at
> >>> vstartup patch then I'm actually going to give my reviewed by on the
> >>> *v1* of this patch (but not this v2):
> >>>
> >>> Reviewed-by: Nicholas Kazlauskas <[e-mail]>
> >>>
> >>> You can feel free to apply that one.
> >>>
> >>> Reason 1: After having thought about it some more I don't think we
> >>> enable anything today that has hubp powered down at the same time we
> >>> expect to be waiting for a flip - eg. DMCU powering down HUBP during PSR
> >>> entry. Static screen interrupt should happen after that flip finishes I
> >>> think.
> >>>
> >>> The CRTC can still be powered on with zero planes, and I don't think any
> >>> userspace explicitly asks for vblank events in this case but it doesn't
> >>> hurt to have the check.
> >>>
> >>> Reason 2: This new patch will need much more thorough testing from side
> >>> to fully understand the consequences of locking the entire DC commit
> >>> sequence. For just a page flip that sounds fine, but for anything more
> >>> than (eg. full updates, modesets, etc) I don't think we want to be
> >>> disabling interrupts for potentially many milliseconds.
> >>
> >> Ah! I was wondering where the attached splat comes from, but I think
> >> this explains it: With this patch amdgpu_dm_commit_planes keeps the
> >> pcrtc->dev->event_lock spinlock locked while calling
> >> dc_commit_updates_for_stream, which ends up calling
> >> smu_set_display_count, which tries to lock a mutex.
> >>
> >>
> >>
> >> _______________________________________________
> >> amd-gfx mailing list
> >> [e-mail]
> >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> >>

Kazlauskas, Nicholas May 5, 2020, 5:59 p.m. UTC | #8

Can you file a full bug report on the gitlab tracker?

FreeSync is still working on my Navi setups with this patch applied, and 
this patch is essentially just a revert of another patch already (where 
FreeSync worked before).

I can understand the v2 of this series causing issues, but the v1 
shouldn't be - so I'd like to understand more about the setup where this 
is causing issues - ASIC, OS, compositor, displays, dmesg log, X log, etc.

Regards,
Nicholas Kazlauskas

On 2020-05-05 1:03 p.m., Alex Deucher wrote:
> Mario or Nick any thoughts?
> 
> Alex
> 
> On Mon, May 4, 2020 at 1:35 PM Matt Coffin <[e-mail]> wrote:
>>
>> Hey guys,
>>
>> This is still an issue for me, and I'm still having to run a patch to
>> revert this as of 5.7-rc4. To avoid breaking a lot of people's Navi
>> setups in 5.7, is there any news on this? Has anyone else at the very
>> least been able to reproduce the problem?
>>
>> It happens for me in every single program that mesa allows to utilize
>> variable refresh rates, and reverting it "fixes" the issue.
>>
>> Cheers, and sorry for the extra email, just making sure this is still on
>> someone's radar,
>> Matt
>>
>> On 4/14/20 5:32 PM, Matt Coffin wrote:
>>> Hey everyone,
>>>
>>> This patch broke variable refresh rate in games (all that I've tried so
>>> far... Project CARS 2, DiRT Rally 2.0, Assetto Corsa Competizione) as
>>> well as a simple freesync tester application.
>>>
>>> FreeSync tester I've been using: https://github.com/Nixola/VRRTest
>>>
>>> I'm not at all familiar with the page flipping code, so it would take me
>>> a long time to find the *right* way to fix it, but does someone else see
>>> why it would do that?
>>>
>>> The symptom is that the refresh rate of the display constantly bounces
>>> between the two ends of the FreeSync range (for me 40 -> 144), and the
>>> game stutters like a madman.
>>>
>>> Any help on where to start, ideas on how to fix it (other than just
>>> revert this commit, which I've done in the interim), or alternative
>>> patches would be appreciated.
>>>
>>> Thanks in advance for the work/help,
>>> Matt
>>>
>>> On 3/13/20 8:42 AM, Michel Dänzer wrote:
>>>> On 2020-03-13 1:35 p.m., Kazlauskas, Nicholas wrote:
>>>>> On 2020-03-12 10:32 a.m., Alex Deucher wrote:
>>>>>> On Thu, Mar 5, 2020 at 4:21 PM Mario Kleiner
>>>>>> <[e-mail]> wrote:
>>>>>>>
>>>>>>> Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
>>>>>>> events at vsartup for DCN")' introduces a new way of pageflip
>>>>>>> completion handling for DCN, and some trouble.
>>>>>>>
>>>>>>> The current implementation introduces a race condition, which
>>>>>>> can cause pageflip completion events to be sent out one vblank
>>>>>>> too early, thereby confusing userspace and causing flicker:
>>>>>>>
>>>>>>> prepare_flip_isr():
>>>>>>>
>>>>>>> 1. Pageflip programming takes the ddev->event_lock.
>>>>>>> 2. Sets acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED
>>>>>>> 3. Releases ddev->event_lock.
>>>>>>>
>>>>>>> --> Deadline for surface address regs double-buffering passes on
>>>>>>>       target pipe.
>>>>>>>
>>>>>>> 4. dc_commit_updates_for_stream() MMIO programs the new pageflip
>>>>>>>      into hw, but too late for current vblank.
>>>>>>>
>>>>>>> => pflip_status == AMDGPU_FLIP_SUBMITTED, but flip won't complete
>>>>>>>      in current vblank due to missing the double-buffering deadline
>>>>>>>      by a tiny bit.
>>>>>>>
>>>>>>> 5. VSTARTUP trigger point in vblank is reached, VSTARTUP irq fires,
>>>>>>>      dm_dcn_crtc_high_irq() gets called.
>>>>>>>
>>>>>>> 6. Detects pflip_status == AMDGPU_FLIP_SUBMITTED and assumes the
>>>>>>>      pageflip has been completed/will complete in this vblank and
>>>>>>>      sends out pageflip completion event to userspace and resets
>>>>>>>      pflip_status = AMDGPU_FLIP_NONE.
>>>>>>>
>>>>>>> => Flip completion event sent out one vblank too early.
>>>>>>>
>>>>>>> This behaviour has been observed during my testing with measurement
>>>>>>> hardware a couple of time.
>>>>>>>
>>>>>>> The commit message says that the extra flip event code was added to
>>>>>>> dm_dcn_crtc_high_irq() to prevent missing to send out pageflip events
>>>>>>> in case the pflip irq doesn't fire, because the "DCH HUBP" component
>>>>>>> is clock gated and doesn't fire pflip irqs in that state. Also that
>>>>>>> this clock gating may happen if no planes are active. According to
>>>>>>> Nicholas, the clock gating can also happen if psr is active, and the
>>>>>>> gating is controlled independently by the hardware, so difficult to
>>>>>>> detect if and when the completion code in above commit is needed.
>>>>>>>
>>>>>>> This patch tries the following solution: It only executes the extra
>>>>>>> pflip
>>>>>>> completion code in dm_dcn_crtc_high_irq() iff the hardware reports
>>>>>>> that there aren't any surface updated pending in the double-buffered
>>>>>>> surface scanout address registers. Otherwise it leaves pflip completion
>>>>>>> to the pflip irq handler, for a more race-free experience.
>>>>>>>
>>>>>>> This would only guard against the order of events mentioned above.
>>>>>>> If Step 5 (VSTARTUP trigger) happens before step 4 then this won't help
>>>>>>> at all, because 1-3 + 5 might happen even without the hw being
>>>>>>> programmed
>>>>>>> at all, ie. no surface update pending because none yet programmed
>>>>>>> into hw.
>>>>>>>
>>>>>>> Therefore this patch also changes locking in amdgpu_dm_commit_planes(),
>>>>>>> so that prepare_flip_isr() and dc_commit_updates_for_stream() are done
>>>>>>> under event_lock protection within the same critical section.
>>>>>>>
>>>>>>> v2: Take Nicholas comments into account, try a different solution.
>>>>>>>
>>>>>>> Lightly tested on Polaris (locking) and Raven (the whole DCN stuff).
>>>>>>> Seems to work without causing obvious new trouble.
>>>>>>
>>>>>> Nick, any comments on this?  Can we get this committed or do you think
>>>>>> it needs additional rework?
>>>>>>
>>>>>> Thanks,
>>>>>>
>>>>>> Alex
>>>>>
>>>>> Hi Alex, Mario,
>>>>>
>>>>> This might be a little strange, but if we want to get this in as a fix
>>>>> for regressions caused by the original vblank and user events at
>>>>> vstartup patch then I'm actually going to give my reviewed by on the
>>>>> *v1* of this patch (but not this v2):
>>>>>
>>>>> Reviewed-by: Nicholas Kazlauskas <[e-mail]>
>>>>>
>>>>> You can feel free to apply that one.
>>>>>
>>>>> Reason 1: After having thought about it some more I don't think we
>>>>> enable anything today that has hubp powered down at the same time we
>>>>> expect to be waiting for a flip - eg. DMCU powering down HUBP during PSR
>>>>> entry. Static screen interrupt should happen after that flip finishes I
>>>>> think.
>>>>>
>>>>> The CRTC can still be powered on with zero planes, and I don't think any
>>>>> userspace explicitly asks for vblank events in this case but it doesn't
>>>>> hurt to have the check.
>>>>>
>>>>> Reason 2: This new patch will need much more thorough testing from side
>>>>> to fully understand the consequences of locking the entire DC commit
>>>>> sequence. For just a page flip that sounds fine, but for anything more
>>>>> than (eg. full updates, modesets, etc) I don't think we want to be
>>>>> disabling interrupts for potentially many milliseconds.
>>>>
>>>> Ah! I was wondering where the attached splat comes from, but I think
>>>> this explains it: With this patch amdgpu_dm_commit_planes keeps the
>>>> pcrtc->dev->event_lock spinlock locked while calling
>>>> dc_commit_updates_for_stream, which ends up calling
>>>> smu_set_display_count, which tries to lock a mutex.
>>>>
>>>>
>>>>
>>>> _______________________________________________
>>>> amd-gfx mailing list
>>>> [e-mail]
>>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>>>

Matt Coffin May 5, 2020, 6:03 p.m. UTC | #9

Sure, I'll file one after work today.

To clarify though, FreeSync still "works" as in the monitor refresh rate
is updating, but it constantly bounces between the maximum and minimum
freesync refresh rates, causing it to look VERY stuttery.

Thanks for the attention, I'll file the but tonight. If you want another
reference person, it got a little discussion in this bug report...

https://gitlab.freedesktop.org/drm/amd/-/issues/1002#note_486494

Cheers,
Matt


On 5/5/20 11:59 AM, Kazlauskas, Nicholas wrote:
> Can you file a full bug report on the gitlab tracker?
> 
> FreeSync is still working on my Navi setups with this patch applied, and
> this patch is essentially just a revert of another patch already (where
> FreeSync worked before).
> 
> I can understand the v2 of this series causing issues, but the v1
> shouldn't be - so I'd like to understand more about the setup where this
> is causing issues - ASIC, OS, compositor, displays, dmesg log, X log, etc.
> 
> Regards,
> Nicholas Kazlauskas
> 
> On 2020-05-05 1:03 p.m., Alex Deucher wrote:
>> Mario or Nick any thoughts?
>>
>> Alex
>>
>> On Mon, May 4, 2020 at 1:35 PM Matt Coffin <[e-mail]> wrote:
>>>
>>> Hey guys,
>>>
>>> This is still an issue for me, and I'm still having to run a patch to
>>> revert this as of 5.7-rc4. To avoid breaking a lot of people's Navi
>>> setups in 5.7, is there any news on this? Has anyone else at the very
>>> least been able to reproduce the problem?
>>>
>>> It happens for me in every single program that mesa allows to utilize
>>> variable refresh rates, and reverting it "fixes" the issue.
>>>
>>> Cheers, and sorry for the extra email, just making sure this is still on
>>> someone's radar,
>>> Matt
>>>
>>> On 4/14/20 5:32 PM, Matt Coffin wrote:
>>>> Hey everyone,
>>>>
>>>> This patch broke variable refresh rate in games (all that I've tried so
>>>> far... Project CARS 2, DiRT Rally 2.0, Assetto Corsa Competizione) as
>>>> well as a simple freesync tester application.
>>>>
>>>> FreeSync tester I've been using: https://github.com/Nixola/VRRTest
>>>>
>>>> I'm not at all familiar with the page flipping code, so it would
>>>> take me
>>>> a long time to find the *right* way to fix it, but does someone else
>>>> see
>>>> why it would do that?
>>>>
>>>> The symptom is that the refresh rate of the display constantly bounces
>>>> between the two ends of the FreeSync range (for me 40 -> 144), and the
>>>> game stutters like a madman.
>>>>
>>>> Any help on where to start, ideas on how to fix it (other than just
>>>> revert this commit, which I've done in the interim), or alternative
>>>> patches would be appreciated.
>>>>
>>>> Thanks in advance for the work/help,
>>>> Matt
>>>>
>>>> On 3/13/20 8:42 AM, Michel Dänzer wrote:
>>>>> On 2020-03-13 1:35 p.m., Kazlauskas, Nicholas wrote:
>>>>>> On 2020-03-12 10:32 a.m., Alex Deucher wrote:
>>>>>>> On Thu, Mar 5, 2020 at 4:21 PM Mario Kleiner
>>>>>>> <[e-mail]> wrote:
>>>>>>>>
>>>>>>>> Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
>>>>>>>> events at vsartup for DCN")' introduces a new way of pageflip
>>>>>>>> completion handling for DCN, and some trouble.
>>>>>>>>
>>>>>>>> The current implementation introduces a race condition, which
>>>>>>>> can cause pageflip completion events to be sent out one vblank
>>>>>>>> too early, thereby confusing userspace and causing flicker:
>>>>>>>>
>>>>>>>> prepare_flip_isr():
>>>>>>>>
>>>>>>>> 1. Pageflip programming takes the ddev->event_lock.
>>>>>>>> 2. Sets acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED
>>>>>>>> 3. Releases ddev->event_lock.
>>>>>>>>
>>>>>>>> --> Deadline for surface address regs double-buffering passes on
>>>>>>>>       target pipe.
>>>>>>>>
>>>>>>>> 4. dc_commit_updates_for_stream() MMIO programs the new pageflip
>>>>>>>>      into hw, but too late for current vblank.
>>>>>>>>
>>>>>>>> => pflip_status == AMDGPU_FLIP_SUBMITTED, but flip won't complete
>>>>>>>>      in current vblank due to missing the double-buffering deadline
>>>>>>>>      by a tiny bit.
>>>>>>>>
>>>>>>>> 5. VSTARTUP trigger point in vblank is reached, VSTARTUP irq fires,
>>>>>>>>      dm_dcn_crtc_high_irq() gets called.
>>>>>>>>
>>>>>>>> 6. Detects pflip_status == AMDGPU_FLIP_SUBMITTED and assumes the
>>>>>>>>      pageflip has been completed/will complete in this vblank and
>>>>>>>>      sends out pageflip completion event to userspace and resets
>>>>>>>>      pflip_status = AMDGPU_FLIP_NONE.
>>>>>>>>
>>>>>>>> => Flip completion event sent out one vblank too early.
>>>>>>>>
>>>>>>>> This behaviour has been observed during my testing with measurement
>>>>>>>> hardware a couple of time.
>>>>>>>>
>>>>>>>> The commit message says that the extra flip event code was added to
>>>>>>>> dm_dcn_crtc_high_irq() to prevent missing to send out pageflip
>>>>>>>> events
>>>>>>>> in case the pflip irq doesn't fire, because the "DCH HUBP"
>>>>>>>> component
>>>>>>>> is clock gated and doesn't fire pflip irqs in that state. Also that
>>>>>>>> this clock gating may happen if no planes are active. According to
>>>>>>>> Nicholas, the clock gating can also happen if psr is active, and
>>>>>>>> the
>>>>>>>> gating is controlled independently by the hardware, so difficult to
>>>>>>>> detect if and when the completion code in above commit is needed.
>>>>>>>>
>>>>>>>> This patch tries the following solution: It only executes the extra
>>>>>>>> pflip
>>>>>>>> completion code in dm_dcn_crtc_high_irq() iff the hardware reports
>>>>>>>> that there aren't any surface updated pending in the
>>>>>>>> double-buffered
>>>>>>>> surface scanout address registers. Otherwise it leaves pflip
>>>>>>>> completion
>>>>>>>> to the pflip irq handler, for a more race-free experience.
>>>>>>>>
>>>>>>>> This would only guard against the order of events mentioned above.
>>>>>>>> If Step 5 (VSTARTUP trigger) happens before step 4 then this
>>>>>>>> won't help
>>>>>>>> at all, because 1-3 + 5 might happen even without the hw being
>>>>>>>> programmed
>>>>>>>> at all, ie. no surface update pending because none yet programmed
>>>>>>>> into hw.
>>>>>>>>
>>>>>>>> Therefore this patch also changes locking in
>>>>>>>> amdgpu_dm_commit_planes(),
>>>>>>>> so that prepare_flip_isr() and dc_commit_updates_for_stream()
>>>>>>>> are done
>>>>>>>> under event_lock protection within the same critical section.
>>>>>>>>
>>>>>>>> v2: Take Nicholas comments into account, try a different solution.
>>>>>>>>
>>>>>>>> Lightly tested on Polaris (locking) and Raven (the whole DCN
>>>>>>>> stuff).
>>>>>>>> Seems to work without causing obvious new trouble.
>>>>>>>
>>>>>>> Nick, any comments on this?  Can we get this committed or do you
>>>>>>> think
>>>>>>> it needs additional rework?
>>>>>>>
>>>>>>> Thanks,
>>>>>>>
>>>>>>> Alex
>>>>>>
>>>>>> Hi Alex, Mario,
>>>>>>
>>>>>> This might be a little strange, but if we want to get this in as a
>>>>>> fix
>>>>>> for regressions caused by the original vblank and user events at
>>>>>> vstartup patch then I'm actually going to give my reviewed by on the
>>>>>> *v1* of this patch (but not this v2):
>>>>>>
>>>>>> Reviewed-by: Nicholas Kazlauskas <[e-mail]>
>>>>>>
>>>>>> You can feel free to apply that one.
>>>>>>
>>>>>> Reason 1: After having thought about it some more I don't think we
>>>>>> enable anything today that has hubp powered down at the same time we
>>>>>> expect to be waiting for a flip - eg. DMCU powering down HUBP
>>>>>> during PSR
>>>>>> entry. Static screen interrupt should happen after that flip
>>>>>> finishes I
>>>>>> think.
>>>>>>
>>>>>> The CRTC can still be powered on with zero planes, and I don't
>>>>>> think any
>>>>>> userspace explicitly asks for vblank events in this case but it
>>>>>> doesn't
>>>>>> hurt to have the check.
>>>>>>
>>>>>> Reason 2: This new patch will need much more thorough testing from
>>>>>> side
>>>>>> to fully understand the consequences of locking the entire DC commit
>>>>>> sequence. For just a page flip that sounds fine, but for anything
>>>>>> more
>>>>>> than (eg. full updates, modesets, etc) I don't think we want to be
>>>>>> disabling interrupts for potentially many milliseconds.
>>>>>
>>>>> Ah! I was wondering where the attached splat comes from, but I think
>>>>> this explains it: With this patch amdgpu_dm_commit_planes keeps the
>>>>> pcrtc->dev->event_lock spinlock locked while calling
>>>>> dc_commit_updates_for_stream, which ends up calling
>>>>> smu_set_display_count, which tries to lock a mutex.
>>>>>
>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> amd-gfx mailing list
>>>>> [e-mail]
>>>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>>>>
>

Matt Coffin May 8, 2020, 3:54 p.m. UTC | #10

Just to follow up on this, I decided not to file the report, since
Nick's latest patch that "Fixes:" this has fixed my issue. Thanks for
the good work on that one Nick.

Might want to make sure that makes it in to the 5.7 fixes :)

Thanks again guys.

~Matt

On 5/5/20 11:59 AM, Kazlauskas, Nicholas wrote:
> Can you file a full bug report on the gitlab tracker?
> 
> FreeSync is still working on my Navi setups with this patch applied, and
> this patch is essentially just a revert of another patch already (where
> FreeSync worked before).
> 
> I can understand the v2 of this series causing issues, but the v1
> shouldn't be - so I'd like to understand more about the setup where this
> is causing issues - ASIC, OS, compositor, displays, dmesg log, X log, etc.
> 
> Regards,
> Nicholas Kazlauskas
> 
> On 2020-05-05 1:03 p.m., Alex Deucher wrote:
>> Mario or Nick any thoughts?
>>
>> Alex
>>
>> On Mon, May 4, 2020 at 1:35 PM Matt Coffin <[e-mail]> wrote:
>>>
>>> Hey guys,
>>>
>>> This is still an issue for me, and I'm still having to run a patch to
>>> revert this as of 5.7-rc4. To avoid breaking a lot of people's Navi
>>> setups in 5.7, is there any news on this? Has anyone else at the very
>>> least been able to reproduce the problem?
>>>
>>> It happens for me in every single program that mesa allows to utilize
>>> variable refresh rates, and reverting it "fixes" the issue.
>>>
>>> Cheers, and sorry for the extra email, just making sure this is still on
>>> someone's radar,
>>> Matt
>>>
>>> On 4/14/20 5:32 PM, Matt Coffin wrote:
>>>> Hey everyone,
>>>>
>>>> This patch broke variable refresh rate in games (all that I've tried so
>>>> far... Project CARS 2, DiRT Rally 2.0, Assetto Corsa Competizione) as
>>>> well as a simple freesync tester application.
>>>>
>>>> FreeSync tester I've been using: https://github.com/Nixola/VRRTest
>>>>
>>>> I'm not at all familiar with the page flipping code, so it would
>>>> take me
>>>> a long time to find the *right* way to fix it, but does someone else
>>>> see
>>>> why it would do that?
>>>>
>>>> The symptom is that the refresh rate of the display constantly bounces
>>>> between the two ends of the FreeSync range (for me 40 -> 144), and the
>>>> game stutters like a madman.
>>>>
>>>> Any help on where to start, ideas on how to fix it (other than just
>>>> revert this commit, which I've done in the interim), or alternative
>>>> patches would be appreciated.
>>>>
>>>> Thanks in advance for the work/help,
>>>> Matt
>>>>
>>>> On 3/13/20 8:42 AM, Michel Dänzer wrote:
>>>>> On 2020-03-13 1:35 p.m., Kazlauskas, Nicholas wrote:
>>>>>> On 2020-03-12 10:32 a.m., Alex Deucher wrote:
>>>>>>> On Thu, Mar 5, 2020 at 4:21 PM Mario Kleiner
>>>>>>> <[e-mail]> wrote:
>>>>>>>>
>>>>>>>> Commit '16f17eda8bad ("drm/amd/display: Send vblank and user
>>>>>>>> events at vsartup for DCN")' introduces a new way of pageflip
>>>>>>>> completion handling for DCN, and some trouble.
>>>>>>>>
>>>>>>>> The current implementation introduces a race condition, which
>>>>>>>> can cause pageflip completion events to be sent out one vblank
>>>>>>>> too early, thereby confusing userspace and causing flicker:
>>>>>>>>
>>>>>>>> prepare_flip_isr():
>>>>>>>>
>>>>>>>> 1. Pageflip programming takes the ddev->event_lock.
>>>>>>>> 2. Sets acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED
>>>>>>>> 3. Releases ddev->event_lock.
>>>>>>>>
>>>>>>>> --> Deadline for surface address regs double-buffering passes on
>>>>>>>>       target pipe.
>>>>>>>>
>>>>>>>> 4. dc_commit_updates_for_stream() MMIO programs the new pageflip
>>>>>>>>      into hw, but too late for current vblank.
>>>>>>>>
>>>>>>>> => pflip_status == AMDGPU_FLIP_SUBMITTED, but flip won't complete
>>>>>>>>      in current vblank due to missing the double-buffering deadline
>>>>>>>>      by a tiny bit.
>>>>>>>>
>>>>>>>> 5. VSTARTUP trigger point in vblank is reached, VSTARTUP irq fires,
>>>>>>>>      dm_dcn_crtc_high_irq() gets called.
>>>>>>>>
>>>>>>>> 6. Detects pflip_status == AMDGPU_FLIP_SUBMITTED and assumes the
>>>>>>>>      pageflip has been completed/will complete in this vblank and
>>>>>>>>      sends out pageflip completion event to userspace and resets
>>>>>>>>      pflip_status = AMDGPU_FLIP_NONE.
>>>>>>>>
>>>>>>>> => Flip completion event sent out one vblank too early.
>>>>>>>>
>>>>>>>> This behaviour has been observed during my testing with measurement
>>>>>>>> hardware a couple of time.
>>>>>>>>
>>>>>>>> The commit message says that the extra flip event code was added to
>>>>>>>> dm_dcn_crtc_high_irq() to prevent missing to send out pageflip
>>>>>>>> events
>>>>>>>> in case the pflip irq doesn't fire, because the "DCH HUBP"
>>>>>>>> component
>>>>>>>> is clock gated and doesn't fire pflip irqs in that state. Also that
>>>>>>>> this clock gating may happen if no planes are active. According to
>>>>>>>> Nicholas, the clock gating can also happen if psr is active, and
>>>>>>>> the
>>>>>>>> gating is controlled independently by the hardware, so difficult to
>>>>>>>> detect if and when the completion code in above commit is needed.
>>>>>>>>
>>>>>>>> This patch tries the following solution: It only executes the extra
>>>>>>>> pflip
>>>>>>>> completion code in dm_dcn_crtc_high_irq() iff the hardware reports
>>>>>>>> that there aren't any surface updated pending in the
>>>>>>>> double-buffered
>>>>>>>> surface scanout address registers. Otherwise it leaves pflip
>>>>>>>> completion
>>>>>>>> to the pflip irq handler, for a more race-free experience.
>>>>>>>>
>>>>>>>> This would only guard against the order of events mentioned above.
>>>>>>>> If Step 5 (VSTARTUP trigger) happens before step 4 then this
>>>>>>>> won't help
>>>>>>>> at all, because 1-3 + 5 might happen even without the hw being
>>>>>>>> programmed
>>>>>>>> at all, ie. no surface update pending because none yet programmed
>>>>>>>> into hw.
>>>>>>>>
>>>>>>>> Therefore this patch also changes locking in
>>>>>>>> amdgpu_dm_commit_planes(),
>>>>>>>> so that prepare_flip_isr() and dc_commit_updates_for_stream()
>>>>>>>> are done
>>>>>>>> under event_lock protection within the same critical section.
>>>>>>>>
>>>>>>>> v2: Take Nicholas comments into account, try a different solution.
>>>>>>>>
>>>>>>>> Lightly tested on Polaris (locking) and Raven (the whole DCN
>>>>>>>> stuff).
>>>>>>>> Seems to work without causing obvious new trouble.
>>>>>>>
>>>>>>> Nick, any comments on this?  Can we get this committed or do you
>>>>>>> think
>>>>>>> it needs additional rework?
>>>>>>>
>>>>>>> Thanks,
>>>>>>>
>>>>>>> Alex
>>>>>>
>>>>>> Hi Alex, Mario,
>>>>>>
>>>>>> This might be a little strange, but if we want to get this in as a
>>>>>> fix
>>>>>> for regressions caused by the original vblank and user events at
>>>>>> vstartup patch then I'm actually going to give my reviewed by on the
>>>>>> *v1* of this patch (but not this v2):
>>>>>>
>>>>>> Reviewed-by: Nicholas Kazlauskas <[e-mail]>
>>>>>>
>>>>>> You can feel free to apply that one.
>>>>>>
>>>>>> Reason 1: After having thought about it some more I don't think we
>>>>>> enable anything today that has hubp powered down at the same time we
>>>>>> expect to be waiting for a flip - eg. DMCU powering down HUBP
>>>>>> during PSR
>>>>>> entry. Static screen interrupt should happen after that flip
>>>>>> finishes I
>>>>>> think.
>>>>>>
>>>>>> The CRTC can still be powered on with zero planes, and I don't
>>>>>> think any
>>>>>> userspace explicitly asks for vblank events in this case but it
>>>>>> doesn't
>>>>>> hurt to have the check.
>>>>>>
>>>>>> Reason 2: This new patch will need much more thorough testing from
>>>>>> side
>>>>>> to fully understand the consequences of locking the entire DC commit
>>>>>> sequence. For just a page flip that sounds fine, but for anything
>>>>>> more
>>>>>> than (eg. full updates, modesets, etc) I don't think we want to be
>>>>>> disabling interrupts for potentially many milliseconds.
>>>>>
>>>>> Ah! I was wondering where the attached splat comes from, but I think
>>>>> this explains it: With this patch amdgpu_dm_commit_planes keeps the
>>>>> pcrtc->dev->event_lock spinlock locked while calling
>>>>> dc_commit_updates_for_stream, which ends up calling
>>>>> smu_set_display_count, which tries to lock a mutex.
>>>>>
>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> amd-gfx mailing list
>>>>> [e-mail]
>>>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>>>>
>

Patch

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d7df1a85e72f..aa4e941b276f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -287,6 +287,28 @@  static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
 	       dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
 }
 
+/**
+ * dm_crtc_is_flip_pending() - Is a pageflip pending on this crtc?
+ *
+ * Returns true if any plane on the crtc has a flip pending, false otherwise.
+ */
+static bool dm_crtc_is_flip_pending(struct dm_crtc_state *acrtc_state)
+{
+	struct dc_stream_status *status = dc_stream_get_status(acrtc_state->stream);
+	const struct dc_plane_status *plane_status;
+	int i;
+	bool pending = false;
+
+	for (i = 0; i < status->plane_count; i++) {
+		plane_status = dc_plane_get_status(status->plane_states[i]);
+		pending |= plane_status->is_flip_pending;
+		DRM_DEBUG_DRIVER("plane:%d, flip_pending=%d\n",
+				 i, plane_status->is_flip_pending);
+	}
+
+	return pending;
+}
+
 /**
  * dm_pflip_high_irq() - Handle pageflip interrupt
  * @interrupt_params: ignored
@@ -435,6 +457,11 @@  static void dm_vupdate_high_irq(void *interrupt_params)
 				spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 			}
 		}
+
+		if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
+			DRM_DEBUG_DRIVER("%s:crtc:%d, flip_pending=%d\n", __func__,
+					    acrtc->crtc_id, dm_crtc_is_flip_pending(acrtc_state));
+		}
 	}
 }
 
@@ -489,6 +516,11 @@  static void dm_crtc_high_irq(void *interrupt_params)
 				&acrtc_state->vrr_params.adjust);
 			spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 		}
+
+		if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
+			DRM_DEBUG_DRIVER("%s:crtc:%d, flip_pending=%d\n", __func__,
+					 acrtc->crtc_id, dm_crtc_is_flip_pending(acrtc_state));
+		}
 	}
 }
 
@@ -543,13 +575,29 @@  static void dm_dcn_crtc_high_irq(void *interrupt_params)
 			&acrtc_state->vrr_params.adjust);
 	}
 
-	if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
+	/*
+	 * If there aren't any active_planes, or PSR is active, then DCH HUBP
+	 * may be clock-gated. In that state, pageflip completion interrupts
+	 * won't fire and pageflip completion events won't get delivered.
+	 *
+	 * Prevent this by sending pending pageflip events from here if a flip
+	 * has been submitted, but is no longer pending in hw, ie. has already
+	 * completed.
+	 *
+	 * If the flip is still pending in hw, then use dm_pflip_high_irq()
+	 * instead, handling completion as usual by pflip irq.
+	 */
+	if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
+	    !dm_crtc_is_flip_pending(acrtc_state)) {
 		if (acrtc->event) {
 			drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 			acrtc->event = NULL;
 			drm_crtc_vblank_put(&acrtc->base);
 		}
 		acrtc->pflip_status = AMDGPU_FLIP_NONE;
+
+		DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_NONE\n",
+				 acrtc->crtc_id);
 	}
 
 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
@@ -6325,7 +6373,7 @@  static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 			to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
 	int planes_count = 0, vpos, hpos;
 	long r;
-	unsigned long flags;
+	unsigned long flags = 0;
 	struct amdgpu_bo *abo;
 	uint64_t tiling_flags;
 	uint32_t target_vblank, last_flip_vblank;
@@ -6513,17 +6561,6 @@  static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 			usleep_range(1000, 1100);
 		}
 
-		if (acrtc_attach->base.state->event) {
-			drm_crtc_vblank_get(pcrtc);
-
-			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
-
-			WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
-			prepare_flip_isr(acrtc_attach);
-
-			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
-		}
-
 		if (acrtc_state->stream) {
 			if (acrtc_state->freesync_vrr_info_changed)
 				bundle->stream_update.vrr_infopacket =
@@ -6575,6 +6612,15 @@  static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 				acrtc_state->stream->link->psr_allow_active)
 			amdgpu_dm_psr_disable(acrtc_state->stream);
 
+		if (pflip_present && acrtc_attach->base.state->event) {
+			drm_crtc_vblank_get(pcrtc);
+
+			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
+
+			WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
+			prepare_flip_isr(acrtc_attach);
+		}
+
 		dc_commit_updates_for_stream(dm->dc,
 						     bundle->surface_updates,
 						     planes_count,
@@ -6582,6 +6628,14 @@  static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 						     &bundle->stream_update,
 						     dc_state);
 
+		/*
+		 * Must event_lock protect prepare_flip_isr() above and
+		 * dc_commit_updates_for_stream within same critical section,
+		 * or pageflip completion will suffer bad races on DCN.
+		 */
+		if (pflip_present && acrtc_attach->pflip_status == AMDGPU_FLIP_SUBMITTED)
+			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
+
 		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
 						acrtc_state->stream->psr_version &&
 						!acrtc_state->stream->link->psr_feature_enabled)