diff mbox series

[3/3] drm/i915: Use indirect ctx bb to mend CMD_BUF_CCTL

Message ID 20200417144429.20575-3-mika.kuoppala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [1/3] drm/i915: Add per ctx batchbuffer wa for timestamp | expand

Commit Message

Mika Kuoppala April 17, 2020, 2:44 p.m. UTC 
Use indirect ctx bb to load cmd buffer control value
from context image to avoid corruption.

Testcase: igt/i915_selftest/gt_lrc
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c     | 13 +++++++++++--
 drivers/gpu/drm/i915/gt/intel_lrc_reg.h |  1 +
 drivers/gpu/drm/i915/i915_reg.h         |  1 +
 3 files changed, 13 insertions(+), 2 deletions(-)

Comments

Chris Wilson April 17, 2020, 2:55 p.m. UTC | #1 
Quoting Mika Kuoppala (2020-04-17 15:44:29)
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> index bb444614f33b..6c81a3a815ac 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
> @@ -27,6 +27,7 @@
>  #define CTX_PDP0_UDW                   (0x30 + 1)
>  #define CTX_PDP0_LDW                   (0x32 + 1)
>  #define CTX_R_PWR_CLK_STATE            (0x42 + 1)
> +#define CTX_CMD_BUF_CCTL               (0xB6 + 1)

Can you add this to live_lrc_layout to confirm its location?
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 531884b9050c..45e07209ddf3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3207,7 +3207,7 @@  gen12_emit_timestamp_wa_lrm(struct intel_context *ce, u32 *cs)
 }
 
 static u32 *
-gen12_emit_timestamp_wa_lrr(struct intel_context *ce, u32 *cs)
+gen12_emit_render_ctx_wa(struct intel_context *ce, u32 *cs)
 {
 	const u32 lrc_offset = i915_ggtt_offset(ce->state) +
 		LRC_STATE_PN * PAGE_SIZE;
@@ -3228,6 +3228,15 @@  gen12_emit_timestamp_wa_lrr(struct intel_context *ce, u32 *cs)
 	*cs++ = scratch_reg;
 	*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));
 
+	*cs++ = lrm;
+	*cs++ = scratch_reg;
+	*cs++ = lrc_offset + CTX_CMD_BUF_CCTL * sizeof(u32);
+	*cs++ = 0;
+
+	*cs++ = MI_LOAD_REGISTER_REG | MI_LRI_LRM_CS_MMIO;
+	*cs++ = scratch_reg;
+	*cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0));
+
 	return cs;
 }
 
@@ -3280,7 +3289,7 @@  gen12_setup_timestamp_ctx_wa(struct intel_context *ce)
 {
 	if (ce->engine->class == RENDER_CLASS)
 		execlists_setup_indirect_ctx_bb(ce,
-					gen12_emit_timestamp_wa_lrr);
+					gen12_emit_render_ctx_wa);
 	else
 		execlists_setup_indirect_ctx_bb(ce,
 						gen12_emit_timestamp_wa_lrm);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
index bb444614f33b..6c81a3a815ac 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
@@ -27,6 +27,7 @@ 
 #define CTX_PDP0_UDW			(0x30 + 1)
 #define CTX_PDP0_LDW			(0x32 + 1)
 #define CTX_R_PWR_CLK_STATE		(0x42 + 1)
+#define CTX_CMD_BUF_CCTL		(0xB6 + 1)
 
 #define GEN9_CTX_RING_MI_MODE		0x54
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a24e23e9b3d0..b31ca8e4399f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2657,6 +2657,7 @@  static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define RING_DMA_FADD_UDW(base)	_MMIO((base) + 0x60) /* gen8+ */
 #define RING_INSTPM(base)	_MMIO((base) + 0xc0)
 #define RING_MI_MODE(base)	_MMIO((base) + 0x9c)
+#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
 #define INSTPS		_MMIO(0x2070) /* 965+ only */
 #define GEN4_INSTDONE1	_MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
 #define ACTHD_I965	_MMIO(0x2074)