@@ -8,7 +8,6 @@
*/
#include <linux/err.h>
-#include <linux/firmware/imx/types.h>
#include <linux/firmware/imx/ipc.h>
#include <linux/firmware/imx/sci.h>
#include <linux/interrupt.h>
@@ -3,9 +3,9 @@
* Copyright 2018-2020 NXP.
*/
+#include <dt-bindings/firmware/imx/rsrc.h>
#include <linux/err.h>
#include <linux/firmware/imx/sci.h>
-#include <linux/firmware/imx/types.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
@@ -547,4 +547,88 @@
#define IMX_SC_R_ATTESTATION 545
#define IMX_SC_R_LAST 546
+/*
+ * Defines for SC PM CLK
+ */
+#define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */
+#define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */
+#define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */
+#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */
+#define IMX_SC_PM_CLK_MISC 4 /* Misc clock */
+#define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */
+#define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */
+#define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */
+#define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */
+#define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */
+#define IMX_SC_PM_CLK_CPU 2 /* CPU clock */
+#define IMX_SC_PM_CLK_PLL 4 /* PLL */
+#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */
+
+/*
+ * Defines for SC CONTROL
+ */
+#define IMX_SC_C_TEMP 0U
+#define IMX_SC_C_TEMP_HI 1U
+#define IMX_SC_C_TEMP_LOW 2U
+#define IMX_SC_C_PXL_LINK_MST1_ADDR 3U
+#define IMX_SC_C_PXL_LINK_MST2_ADDR 4U
+#define IMX_SC_C_PXL_LINK_MST_ENB 5U
+#define IMX_SC_C_PXL_LINK_MST1_ENB 6U
+#define IMX_SC_C_PXL_LINK_MST2_ENB 7U
+#define IMX_SC_C_PXL_LINK_SLV1_ADDR 8U
+#define IMX_SC_C_PXL_LINK_SLV2_ADDR 9U
+#define IMX_SC_C_PXL_LINK_MST_VLD 10U
+#define IMX_SC_C_PXL_LINK_MST1_VLD 11U
+#define IMX_SC_C_PXL_LINK_MST2_VLD 12U
+#define IMX_SC_C_SINGLE_MODE 13U
+#define IMX_SC_C_ID 14U
+#define IMX_SC_C_PXL_CLK_POLARITY 15U
+#define IMX_SC_C_LINESTATE 16U
+#define IMX_SC_C_PCIE_G_RST 17U
+#define IMX_SC_C_PCIE_BUTTON_RST 18U
+#define IMX_SC_C_PCIE_PERST 19U
+#define IMX_SC_C_PHY_RESET 20U
+#define IMX_SC_C_PXL_LINK_RATE_CORRECTION 21U
+#define IMX_SC_C_PANIC 22U
+#define IMX_SC_C_PRIORITY_GROUP 23U
+#define IMX_SC_C_TXCLK 24U
+#define IMX_SC_C_CLKDIV 25U
+#define IMX_SC_C_DISABLE_50 26U
+#define IMX_SC_C_DISABLE_125 27U
+#define IMX_SC_C_SEL_125 28U
+#define IMX_SC_C_MODE 29U
+#define IMX_SC_C_SYNC_CTRL0 30U
+#define IMX_SC_C_KACHUNK_CNT 31U
+#define IMX_SC_C_KACHUNK_SEL 32U
+#define IMX_SC_C_SYNC_CTRL1 33U
+#define IMX_SC_C_DPI_RESET 34U
+#define IMX_SC_C_MIPI_RESET 35U
+#define IMX_SC_C_DUAL_MODE 36U
+#define IMX_SC_C_VOLTAGE 37U
+#define IMX_SC_C_PXL_LINK_SEL 38U
+#define IMX_SC_C_OFS_SEL 39U
+#define IMX_SC_C_OFS_AUDIO 40U
+#define IMX_SC_C_OFS_PERIPH 41U
+#define IMX_SC_C_OFS_IRQ 42U
+#define IMX_SC_C_RST0 43U
+#define IMX_SC_C_RST1 44U
+#define IMX_SC_C_SEL0 45U
+#define IMX_SC_C_CALIB0 46U
+#define IMX_SC_C_CALIB1 47U
+#define IMX_SC_C_CALIB2 48U
+#define IMX_SC_C_IPG_DEBUG 49U
+#define IMX_SC_C_IPG_DOZE 50U
+#define IMX_SC_C_IPG_WAIT 51U
+#define IMX_SC_C_IPG_STOP 52U
+#define IMX_SC_C_IPG_STOP_MODE 53U
+#define IMX_SC_C_IPG_STOP_ACK 54U
+#define IMX_SC_C_SYNC_CTRL 55U
+#define IMX_SC_C_OFS_AUDIO_ALT 56U
+#define IMX_SC_C_DSP_BYP 57U
+#define IMX_SC_C_CLK_GEN_EN 58U
+#define IMX_SC_C_INTF_SEL 59U
+#define IMX_SC_C_RXC_DLY 60U
+#define IMX_SC_C_TIMER_SEL 61U
+#define IMX_SC_C_LAST 62U
+
#endif /* __DT_BINDINGS_RSCRC_IMX_H */
@@ -11,7 +11,6 @@
#define _SC_SCI_H
#include <linux/firmware/imx/ipc.h>
-#include <linux/firmware/imx/types.h>
#include <linux/firmware/imx/svc/misc.h>
#include <linux/firmware/imx/svc/pm.h>
deleted file mode 100644
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017~2018 NXP
- *
- * Header file containing types used across multiple service APIs.
- */
-
-#ifndef _SC_TYPES_H
-#define _SC_TYPES_H
-
-/*
- * This type is used to indicate a control.
- */
-enum imx_sc_ctrl {
- IMX_SC_C_TEMP = 0,
- IMX_SC_C_TEMP_HI = 1,
- IMX_SC_C_TEMP_LOW = 2,
- IMX_SC_C_PXL_LINK_MST1_ADDR = 3,
- IMX_SC_C_PXL_LINK_MST2_ADDR = 4,
- IMX_SC_C_PXL_LINK_MST_ENB = 5,
- IMX_SC_C_PXL_LINK_MST1_ENB = 6,
- IMX_SC_C_PXL_LINK_MST2_ENB = 7,
- IMX_SC_C_PXL_LINK_SLV1_ADDR = 8,
- IMX_SC_C_PXL_LINK_SLV2_ADDR = 9,
- IMX_SC_C_PXL_LINK_MST_VLD = 10,
- IMX_SC_C_PXL_LINK_MST1_VLD = 11,
- IMX_SC_C_PXL_LINK_MST2_VLD = 12,
- IMX_SC_C_SINGLE_MODE = 13,
- IMX_SC_C_ID = 14,
- IMX_SC_C_PXL_CLK_POLARITY = 15,
- IMX_SC_C_LINESTATE = 16,
- IMX_SC_C_PCIE_G_RST = 17,
- IMX_SC_C_PCIE_BUTTON_RST = 18,
- IMX_SC_C_PCIE_PERST = 19,
- IMX_SC_C_PHY_RESET = 20,
- IMX_SC_C_PXL_LINK_RATE_CORRECTION = 21,
- IMX_SC_C_PANIC = 22,
- IMX_SC_C_PRIORITY_GROUP = 23,
- IMX_SC_C_TXCLK = 24,
- IMX_SC_C_CLKDIV = 25,
- IMX_SC_C_DISABLE_50 = 26,
- IMX_SC_C_DISABLE_125 = 27,
- IMX_SC_C_SEL_125 = 28,
- IMX_SC_C_MODE = 29,
- IMX_SC_C_SYNC_CTRL0 = 30,
- IMX_SC_C_KACHUNK_CNT = 31,
- IMX_SC_C_KACHUNK_SEL = 32,
- IMX_SC_C_SYNC_CTRL1 = 33,
- IMX_SC_C_DPI_RESET = 34,
- IMX_SC_C_MIPI_RESET = 35,
- IMX_SC_C_DUAL_MODE = 36,
- IMX_SC_C_VOLTAGE = 37,
- IMX_SC_C_PXL_LINK_SEL = 38,
- IMX_SC_C_OFS_SEL = 39,
- IMX_SC_C_OFS_AUDIO = 40,
- IMX_SC_C_OFS_PERIPH = 41,
- IMX_SC_C_OFS_IRQ = 42,
- IMX_SC_C_RST0 = 43,
- IMX_SC_C_RST1 = 44,
- IMX_SC_C_SEL0 = 45,
- IMX_SC_C_LAST
-};
-
-#endif /* _SC_TYPES_H */