| Message ID | 1587726554-32018-3-git-send-email-sumit.garg@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: Introduce new IPI as IPI_CALL_NMI_FUNC | expand |
On Fri, 24 Apr 2020 16:39:12 +0530 Sumit Garg <sumit.garg@linaro.org> wrote: Hi Sumit, > With pseudo NMIs enabled, interrupt controller can be configured to > deliver SGI as a pseudo NMI. So add corresponding handling for SGIs. > > Signed-off-by: Sumit Garg <sumit.garg@linaro.org> > --- > drivers/irqchip/irq-gic-v3.c | 22 +++++++++++++++++----- > 1 file changed, 17 insertions(+), 5 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index d7006ef..be361bf 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -609,17 +609,29 @@ static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) > if (irqs_enabled) > nmi_enter(); > > - if (static_branch_likely(&supports_deactivate_key)) > - gic_write_eoir(irqnr); > /* > * Leave the PSR.I bit set to prevent other NMIs to be > * received while handling this one. > * PSR.I will be restored when we ERET to the > * interrupted context. > */ > - err = handle_domain_nmi(gic_data.domain, irqnr, regs); > - if (err) > - gic_deactivate_unhandled(irqnr); > + if (likely(irqnr > 15)) { > + if (static_branch_likely(&supports_deactivate_key)) > + gic_write_eoir(irqnr); > + > + err = handle_domain_nmi(gic_data.domain, irqnr, regs); > + if (err) > + gic_deactivate_unhandled(irqnr); > + } else { > + gic_write_eoir(irqnr); > + if (static_branch_likely(&supports_deactivate_key)) > + gic_write_dir(irqnr); > +#ifdef CONFIG_SMP > + handle_IPI(irqnr, regs); > +#else > + WARN_ONCE(true, "Unexpected SGI received!\n"); > +#endif > + } > > if (irqs_enabled) > nmi_exit(); If there is one thing I would like to avoid, it is to add more ugly hacks to the way we handle SGIs. There is very little reason why SGIs should be handled differently from all other interrupts. They have the same properties, and it is only because of the 32bit legacy that we deal with them in such a cumbersome way. Nothing that we cannot fix though. What I would really like to see is first a conversion of the SGIs to normal, full fat interrupts. These interrupts can then be configured as NMI using the normal API. I think Julien had something along these lines (or was that limited to the PMU?). Otherwise, I'll happily help you with that. Thanks, M.
On 2020-04-25 11:29, Marc Zyngier wrote: > On Fri, 24 Apr 2020 16:39:12 +0530 > Sumit Garg <sumit.garg@linaro.org> wrote: > > Hi Sumit, > >> With pseudo NMIs enabled, interrupt controller can be configured to >> deliver SGI as a pseudo NMI. So add corresponding handling for SGIs. >> >> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> >> --- >> drivers/irqchip/irq-gic-v3.c | 22 +++++++++++++++++----- >> 1 file changed, 17 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/irqchip/irq-gic-v3.c >> b/drivers/irqchip/irq-gic-v3.c >> index d7006ef..be361bf 100644 >> --- a/drivers/irqchip/irq-gic-v3.c >> +++ b/drivers/irqchip/irq-gic-v3.c >> @@ -609,17 +609,29 @@ static inline void gic_handle_nmi(u32 irqnr, >> struct pt_regs *regs) >> if (irqs_enabled) >> nmi_enter(); >> >> - if (static_branch_likely(&supports_deactivate_key)) >> - gic_write_eoir(irqnr); >> /* >> * Leave the PSR.I bit set to prevent other NMIs to be >> * received while handling this one. >> * PSR.I will be restored when we ERET to the >> * interrupted context. >> */ >> - err = handle_domain_nmi(gic_data.domain, irqnr, regs); >> - if (err) >> - gic_deactivate_unhandled(irqnr); >> + if (likely(irqnr > 15)) { >> + if (static_branch_likely(&supports_deactivate_key)) >> + gic_write_eoir(irqnr); >> + >> + err = handle_domain_nmi(gic_data.domain, irqnr, regs); >> + if (err) >> + gic_deactivate_unhandled(irqnr); >> + } else { >> + gic_write_eoir(irqnr); >> + if (static_branch_likely(&supports_deactivate_key)) >> + gic_write_dir(irqnr); >> +#ifdef CONFIG_SMP >> + handle_IPI(irqnr, regs); >> +#else >> + WARN_ONCE(true, "Unexpected SGI received!\n"); >> +#endif >> + } >> >> if (irqs_enabled) >> nmi_exit(); > > If there is one thing I would like to avoid, it is to add more ugly > hacks to the way we handle SGIs. There is very little reason why SGIs > should be handled differently from all other interrupts. They have the > same properties, and it is only because of the 32bit legacy that we > deal > with them in such a cumbersome way. Nothing that we cannot fix though. > > What I would really like to see is first a conversion of the SGIs to > normal, full fat interrupts. These interrupts can then be configured as > NMI using the normal API. > > I think Julien had something along these lines (or was that limited to > the PMU?). Otherwise, I'll happily help you with that. OK, to give you an idea of what I am after, here's a small series[1] that can be used as a base (it has been booted exactly *once* on a model, and is thus absolutely perfect ;-). There is still a bit of work to be able to actually request a SGI (they are hard-wired as chained interrupts so far, as this otherwise changes the output of /proc/interrupts, among other things), but you will hopefully see what I'm aiming for. Thanks, M. [1] https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=irq/gic-sgi
Hi Marc, Thanks for your comments and apologies for my delayed response as I was exploring ideas that you have shared. On Sat, 25 Apr 2020 at 20:02, Marc Zyngier <maz@kernel.org> wrote: > > On 2020-04-25 11:29, Marc Zyngier wrote: > > On Fri, 24 Apr 2020 16:39:12 +0530 > > Sumit Garg <sumit.garg@linaro.org> wrote: > > > > Hi Sumit, > > > >> With pseudo NMIs enabled, interrupt controller can be configured to > >> deliver SGI as a pseudo NMI. So add corresponding handling for SGIs. > >> > >> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> > >> --- > >> drivers/irqchip/irq-gic-v3.c | 22 +++++++++++++++++----- > >> 1 file changed, 17 insertions(+), 5 deletions(-) > >> > >> diff --git a/drivers/irqchip/irq-gic-v3.c > >> b/drivers/irqchip/irq-gic-v3.c > >> index d7006ef..be361bf 100644 > >> --- a/drivers/irqchip/irq-gic-v3.c > >> +++ b/drivers/irqchip/irq-gic-v3.c > >> @@ -609,17 +609,29 @@ static inline void gic_handle_nmi(u32 irqnr, > >> struct pt_regs *regs) > >> if (irqs_enabled) > >> nmi_enter(); > >> > >> - if (static_branch_likely(&supports_deactivate_key)) > >> - gic_write_eoir(irqnr); > >> /* > >> * Leave the PSR.I bit set to prevent other NMIs to be > >> * received while handling this one. > >> * PSR.I will be restored when we ERET to the > >> * interrupted context. > >> */ > >> - err = handle_domain_nmi(gic_data.domain, irqnr, regs); > >> - if (err) > >> - gic_deactivate_unhandled(irqnr); > >> + if (likely(irqnr > 15)) { > >> + if (static_branch_likely(&supports_deactivate_key)) > >> + gic_write_eoir(irqnr); > >> + > >> + err = handle_domain_nmi(gic_data.domain, irqnr, regs); > >> + if (err) > >> + gic_deactivate_unhandled(irqnr); > >> + } else { > >> + gic_write_eoir(irqnr); > >> + if (static_branch_likely(&supports_deactivate_key)) > >> + gic_write_dir(irqnr); > >> +#ifdef CONFIG_SMP > >> + handle_IPI(irqnr, regs); > >> +#else > >> + WARN_ONCE(true, "Unexpected SGI received!\n"); > >> +#endif > >> + } > >> > >> if (irqs_enabled) > >> nmi_exit(); > > > > If there is one thing I would like to avoid, it is to add more ugly > > hacks to the way we handle SGIs. There is very little reason why SGIs > > should be handled differently from all other interrupts. They have the > > same properties, and it is only because of the 32bit legacy that we > > deal > > with them in such a cumbersome way. Nothing that we cannot fix though. > > > > What I would really like to see is first a conversion of the SGIs to > > normal, full fat interrupts. These interrupts can then be configured as > > NMI using the normal API. > > > > I think Julien had something along these lines (or was that limited to > > the PMU?). Otherwise, I'll happily help you with that. > > OK, to give you an idea of what I am after, here's a small series[1] > that > can be used as a base (it has been booted exactly *once* on a model, and > is thus absolutely perfect ;-). Thanks for this series. I have re-based my patch-set on top of this series [1] and just dropped this patch #2. It works fine for me. > > There is still a bit of work to be able to actually request a SGI (they > are hard-wired as chained interrupts so far, as this otherwise changes > the output of /proc/interrupts, among other things), but you will > hopefully see what I'm aiming for. I was exploring this idea: "request a SGI". I guess here you meant to request a new SGI as a normal NMI/IRQ via common APIs such as request_percpu_nmi() or request_percpu_irq() rather than statically adding a new IPI as per this patch [2], correct? If yes, then I have following follow up queries: 1. Do you envision any drivers to use SGIs in a similar manner as they use SPIs or PPIs? 2. How do you envision allocation of SGIs as currently they are hardcoded in an arch specific file (like arch/arm64/kernel/smp.c +794)? 3. AFAIK, the major difference among SGIs and SPIs or PPIs is the trigger method where SGIs are software triggered and SPIs or PPIs are hardware triggered. And I couldn't find a generalized method across architectures to invoke SGIs. So how do you envision drivers to invoke SGIs in an architecture agnostic manner? [1] https://git.linaro.org/people/sumit.garg/linux.git/?h=kgdb-nmi [2] https://git.linaro.org/people/sumit.garg/linux.git/commit/?h=kgdb-nmi&id=fc89e5f395f89966110554a15ab0fa0f0d471132 -Sumit > > Thanks, > > M. > > [1] > https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=irq/gic-sgi > -- > Jazz is not dead. It just smells funny...
Hi Sumit, On 2020-04-28 15:11, Sumit Garg wrote: > Hi Marc, > > Thanks for your comments and apologies for my delayed response as I > was exploring ideas that you have shared. > > On Sat, 25 Apr 2020 at 20:02, Marc Zyngier <maz@kernel.org> wrote: >> >> On 2020-04-25 11:29, Marc Zyngier wrote: >> > On Fri, 24 Apr 2020 16:39:12 +0530 >> > Sumit Garg <sumit.garg@linaro.org> wrote: >> > >> > Hi Sumit, >> > >> >> With pseudo NMIs enabled, interrupt controller can be configured to >> >> deliver SGI as a pseudo NMI. So add corresponding handling for SGIs. >> >> >> >> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> >> >> --- >> >> drivers/irqchip/irq-gic-v3.c | 22 +++++++++++++++++----- >> >> 1 file changed, 17 insertions(+), 5 deletions(-) >> >> >> >> diff --git a/drivers/irqchip/irq-gic-v3.c >> >> b/drivers/irqchip/irq-gic-v3.c >> >> index d7006ef..be361bf 100644 >> >> --- a/drivers/irqchip/irq-gic-v3.c >> >> +++ b/drivers/irqchip/irq-gic-v3.c >> >> @@ -609,17 +609,29 @@ static inline void gic_handle_nmi(u32 irqnr, >> >> struct pt_regs *regs) >> >> if (irqs_enabled) >> >> nmi_enter(); >> >> >> >> - if (static_branch_likely(&supports_deactivate_key)) >> >> - gic_write_eoir(irqnr); >> >> /* >> >> * Leave the PSR.I bit set to prevent other NMIs to be >> >> * received while handling this one. >> >> * PSR.I will be restored when we ERET to the >> >> * interrupted context. >> >> */ >> >> - err = handle_domain_nmi(gic_data.domain, irqnr, regs); >> >> - if (err) >> >> - gic_deactivate_unhandled(irqnr); >> >> + if (likely(irqnr > 15)) { >> >> + if (static_branch_likely(&supports_deactivate_key)) >> >> + gic_write_eoir(irqnr); >> >> + >> >> + err = handle_domain_nmi(gic_data.domain, irqnr, regs); >> >> + if (err) >> >> + gic_deactivate_unhandled(irqnr); >> >> + } else { >> >> + gic_write_eoir(irqnr); >> >> + if (static_branch_likely(&supports_deactivate_key)) >> >> + gic_write_dir(irqnr); >> >> +#ifdef CONFIG_SMP >> >> + handle_IPI(irqnr, regs); >> >> +#else >> >> + WARN_ONCE(true, "Unexpected SGI received!\n"); >> >> +#endif >> >> + } >> >> >> >> if (irqs_enabled) >> >> nmi_exit(); >> > >> > If there is one thing I would like to avoid, it is to add more ugly >> > hacks to the way we handle SGIs. There is very little reason why SGIs >> > should be handled differently from all other interrupts. They have the >> > same properties, and it is only because of the 32bit legacy that we >> > deal >> > with them in such a cumbersome way. Nothing that we cannot fix though. >> > >> > What I would really like to see is first a conversion of the SGIs to >> > normal, full fat interrupts. These interrupts can then be configured as >> > NMI using the normal API. >> > >> > I think Julien had something along these lines (or was that limited to >> > the PMU?). Otherwise, I'll happily help you with that. >> >> OK, to give you an idea of what I am after, here's a small series[1] >> that >> can be used as a base (it has been booted exactly *once* on a model, >> and >> is thus absolutely perfect ;-). > > Thanks for this series. I have re-based my patch-set on top of this > series [1] and just dropped this patch #2. It works fine for me. I just had a look. "irqchip/gic-v3: Enable arch specific IPI as pseudo NMI" is still done the wrong way, I'm afraid. You directly poke into the GIC configuration, which isn't acceptable, as you leave the rest of the kernel completely unaware that this is a NMI. You should make the interrupt a NMI as it is being configured in gic_smp_init(), calling request_nmi() at this stage. >> >> There is still a bit of work to be able to actually request a SGI >> (they >> are hard-wired as chained interrupts so far, as this otherwise changes >> the output of /proc/interrupts, among other things), but you will >> hopefully see what I'm aiming for. > > I was exploring this idea: "request a SGI". I guess here you meant to > request a new SGI as a normal NMI/IRQ via common APIs such as > request_percpu_nmi() or request_percpu_irq() rather than statically > adding a new IPI as per this patch [2], correct? If yes, then I have > following follow up queries: > > 1. Do you envision any drivers to use SGIs in a similar manner as they > use SPIs or PPIs? No. SGIs are already pretty much all allocated for the kernel's internal needs and once we allocate an additional one for this KGDB feature, we're out of non-secure SGIs. We could start a multiplexing scheme to overcome this, but the kernel already has plenty of other mechanisms for internal communication. After all, why would you need anything more than smp_call_function()? The single use case I can imagine is that you'd want to signal a CPU that isn't running Linux. This would require a lot more work than just an interrupt, and is out of scope for the time being. > 2. How do you envision allocation of SGIs as currently they are > hardcoded in an arch specific file (like arch/arm64/kernel/smp.c > +794)? What I would like is for the arch code to request these interrupts as normal interrupts, for which there is one problem to solve: how do you find out about the Linux IRQ number for a given IPI. Or rather, how do you get rid of the requirement to have IPI numbers at all and just say "give me a per-cpu interrupt that I can use as an IPI, and by the way here's the handler you can call". And I insist: this is only for the arch code. Nothing else. > 3. AFAIK, the major difference among SGIs and SPIs or PPIs is the > trigger method where SGIs are software triggered and SPIs or PPIs are > hardware triggered. And I couldn't find a generalized method across > architectures to invoke SGIs. So how do you envision drivers to invoke > SGIs in an architecture agnostic manner? Well, SGIs are not architecture agnostic. They are fundamentally part of the GIC architecture, which only exists for the two ARM architectures. SGIs are not a general purpose mechanism. IPIs are, and we have services on top of IPIs, such as invoking a function on a remote CPU. What else do you need? Thanks, M.
Hi Marc, On Wed, 29 Apr 2020 at 13:53, Marc Zyngier <maz@kernel.org> wrote: > > Hi Sumit, > > On 2020-04-28 15:11, Sumit Garg wrote: > > Hi Marc, > > > > Thanks for your comments and apologies for my delayed response as I > > was exploring ideas that you have shared. > > > > On Sat, 25 Apr 2020 at 20:02, Marc Zyngier <maz@kernel.org> wrote: > >> > >> On 2020-04-25 11:29, Marc Zyngier wrote: > >> > On Fri, 24 Apr 2020 16:39:12 +0530 > >> > Sumit Garg <sumit.garg@linaro.org> wrote: > >> > > >> > Hi Sumit, > >> > > >> >> With pseudo NMIs enabled, interrupt controller can be configured to > >> >> deliver SGI as a pseudo NMI. So add corresponding handling for SGIs. > >> >> > >> >> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> > >> >> --- > >> >> drivers/irqchip/irq-gic-v3.c | 22 +++++++++++++++++----- > >> >> 1 file changed, 17 insertions(+), 5 deletions(-) > >> >> > >> >> diff --git a/drivers/irqchip/irq-gic-v3.c > >> >> b/drivers/irqchip/irq-gic-v3.c > >> >> index d7006ef..be361bf 100644 > >> >> --- a/drivers/irqchip/irq-gic-v3.c > >> >> +++ b/drivers/irqchip/irq-gic-v3.c > >> >> @@ -609,17 +609,29 @@ static inline void gic_handle_nmi(u32 irqnr, > >> >> struct pt_regs *regs) > >> >> if (irqs_enabled) > >> >> nmi_enter(); > >> >> > >> >> - if (static_branch_likely(&supports_deactivate_key)) > >> >> - gic_write_eoir(irqnr); > >> >> /* > >> >> * Leave the PSR.I bit set to prevent other NMIs to be > >> >> * received while handling this one. > >> >> * PSR.I will be restored when we ERET to the > >> >> * interrupted context. > >> >> */ > >> >> - err = handle_domain_nmi(gic_data.domain, irqnr, regs); > >> >> - if (err) > >> >> - gic_deactivate_unhandled(irqnr); > >> >> + if (likely(irqnr > 15)) { > >> >> + if (static_branch_likely(&supports_deactivate_key)) > >> >> + gic_write_eoir(irqnr); > >> >> + > >> >> + err = handle_domain_nmi(gic_data.domain, irqnr, regs); > >> >> + if (err) > >> >> + gic_deactivate_unhandled(irqnr); > >> >> + } else { > >> >> + gic_write_eoir(irqnr); > >> >> + if (static_branch_likely(&supports_deactivate_key)) > >> >> + gic_write_dir(irqnr); > >> >> +#ifdef CONFIG_SMP > >> >> + handle_IPI(irqnr, regs); > >> >> +#else > >> >> + WARN_ONCE(true, "Unexpected SGI received!\n"); > >> >> +#endif > >> >> + } > >> >> > >> >> if (irqs_enabled) > >> >> nmi_exit(); > >> > > >> > If there is one thing I would like to avoid, it is to add more ugly > >> > hacks to the way we handle SGIs. There is very little reason why SGIs > >> > should be handled differently from all other interrupts. They have the > >> > same properties, and it is only because of the 32bit legacy that we > >> > deal > >> > with them in such a cumbersome way. Nothing that we cannot fix though. > >> > > >> > What I would really like to see is first a conversion of the SGIs to > >> > normal, full fat interrupts. These interrupts can then be configured as > >> > NMI using the normal API. > >> > > >> > I think Julien had something along these lines (or was that limited to > >> > the PMU?). Otherwise, I'll happily help you with that. > >> > >> OK, to give you an idea of what I am after, here's a small series[1] > >> that > >> can be used as a base (it has been booted exactly *once* on a model, > >> and > >> is thus absolutely perfect ;-). > > > > Thanks for this series. I have re-based my patch-set on top of this > > series [1] and just dropped this patch #2. It works fine for me. > > I just had a look. > > "irqchip/gic-v3: Enable arch specific IPI as pseudo NMI" is still done > the wrong way, I'm afraid. You directly poke into the GIC configuration, > which isn't acceptable, as you leave the rest of the kernel completely > unaware that this is a NMI. You should make the interrupt a NMI as it > is being configured in gic_smp_init(), calling request_nmi() at this > stage. Sure, I will try to follow your suggestion. But I think it's better to first generalize the base IPI allocation scheme. > > >> > >> There is still a bit of work to be able to actually request a SGI > >> (they > >> are hard-wired as chained interrupts so far, as this otherwise changes > >> the output of /proc/interrupts, among other things), but you will > >> hopefully see what I'm aiming for. > > > > I was exploring this idea: "request a SGI". I guess here you meant to > > request a new SGI as a normal NMI/IRQ via common APIs such as > > request_percpu_nmi() or request_percpu_irq() rather than statically > > adding a new IPI as per this patch [2], correct? If yes, then I have > > following follow up queries: > > > > 1. Do you envision any drivers to use SGIs in a similar manner as they > > use SPIs or PPIs? > > No. SGIs are already pretty much all allocated for the kernel's internal > needs and once we allocate an additional one for this KGDB feature, > we're out of non-secure SGIs. We could start a multiplexing scheme to > overcome this, but the kernel already has plenty of other mechanisms > for internal communication. After all, why would you need anything more > than smp_call_function()? > > The single use case I can imagine is that you'd want to signal a CPU > that isn't running Linux. This would require a lot more work than > just an interrupt, and is out of scope for the time being. Thanks for the clarification. > > > 2. How do you envision allocation of SGIs as currently they are > > hardcoded in an arch specific file (like arch/arm64/kernel/smp.c > > +794)? > > What I would like is for the arch code to request these interrupts as > normal interrupts, for which there is one problem to solve: how do you > find out about the Linux IRQ number for a given IPI. Or rather, how > do you get rid of the requirement to have IPI numbers at all and just > say "give me a per-cpu interrupt that I can use as an IPI, and by the > way here's the handler you can call". I think what you are looking for here is something that could be sufficed via enabling "CONFIG_GENERIC_IRQ_IPI" framework for arm64/arm architectures. It's currently used for mips architecture. Looking at its implementation, I think it should be possible to hook up SGIs under new IPI irq_domain for GICv2/v3. So with this framework we should be able to dynamically allocate IPIs and use common APIs such as request_irq()/request_nmi() to tell IPI specific handlers. If this approach looks sane to you then I can start working on a PoC implementation for arm64. > > And I insist: this is only for the arch code. Nothing else. > Makes sense. > > 3. AFAIK, the major difference among SGIs and SPIs or PPIs is the > > trigger method where SGIs are software triggered and SPIs or PPIs are > > hardware triggered. And I couldn't find a generalized method across > > architectures to invoke SGIs. So how do you envision drivers to invoke > > SGIs in an architecture agnostic manner? > > Well, SGIs are not architecture agnostic. They are fundamentally part of > the GIC architecture, which only exists for the two ARM architectures. > > SGIs are not a general purpose mechanism. IPIs are, and we have services > on top of IPIs, such as invoking a function on a remote CPU. What else > do you need? Yeah that was mine understanding as well. But I was just clarifying if you have any further use-cases in mind for IPIs. -Sunit > > Thanks, > > M. > -- > Jazz is not dead. It just smells funny...
On Thu, 30 Apr 2020 12:50:28 +0530 Sumit Garg <sumit.garg@linaro.org> wrote: > Hi Marc, > > On Wed, 29 Apr 2020 at 13:53, Marc Zyngier <maz@kernel.org> wrote: [...] > > What I would like is for the arch code to request these interrupts as > > normal interrupts, for which there is one problem to solve: how do you > > find out about the Linux IRQ number for a given IPI. Or rather, how > > do you get rid of the requirement to have IPI numbers at all and just > > say "give me a per-cpu interrupt that I can use as an IPI, and by the > > way here's the handler you can call". > > I think what you are looking for here is something that could be > sufficed via enabling "CONFIG_GENERIC_IRQ_IPI" framework for arm64/arm > architectures. It's currently used for mips architecture. Looking at > its implementation, I think it should be possible to hook up SGIs > under new IPI irq_domain for GICv2/v3. > > So with this framework we should be able to dynamically allocate IPIs > and use common APIs such as request_irq()/request_nmi() to tell IPI > specific handlers. > > If this approach looks sane to you then I can start working on a PoC > implementation for arm64. I can't say I'm keen. This IPI framework doesn't really work for the GIC: - it requires a separate irqdomain to be able to guarantee that you allocate the hwirq in the SGI range. What is the point? - it creates yet another level of indirection on IPI injection This framework was created to deal with two cases: - systems that can't represent their IPI with a single hwirq spanning all the CPUs - "accelerator cores" that don't run Linux The GIC architecture avoids the first point, and I don't even want to think of the second one. Also, it doesn't solve the initial problem, which is to bootstrap the whole thing. The IPI framework relies on an irqdomain to be created the first place. This would mean teaching the arch code about the intricacies of irqdomains, FW nodes and other terrible things. All things which are better hidden in the GIC drivers (not to mention the other horror stories that are the RPi-2/3 irqchip and the Huawei GIC knock-off). What I have in mind is to replace the set_smp_cross_call() with something that passes the required set of information (interrupt range, at the very least). The only thing that I plan to reuse from the IPI framework is the chip->ipi_send_mask() callback. Thanks, M.
On Thu, 30 Apr 2020 at 14:43, Marc Zyngier <maz@kernel.org> wrote: > > On Thu, 30 Apr 2020 12:50:28 +0530 > Sumit Garg <sumit.garg@linaro.org> wrote: > > > Hi Marc, > > > > On Wed, 29 Apr 2020 at 13:53, Marc Zyngier <maz@kernel.org> wrote: > > [...] > > > > What I would like is for the arch code to request these interrupts as > > > normal interrupts, for which there is one problem to solve: how do you > > > find out about the Linux IRQ number for a given IPI. Or rather, how > > > do you get rid of the requirement to have IPI numbers at all and just > > > say "give me a per-cpu interrupt that I can use as an IPI, and by the > > > way here's the handler you can call". > > > > I think what you are looking for here is something that could be > > sufficed via enabling "CONFIG_GENERIC_IRQ_IPI" framework for arm64/arm > > architectures. It's currently used for mips architecture. Looking at > > its implementation, I think it should be possible to hook up SGIs > > under new IPI irq_domain for GICv2/v3. > > > > So with this framework we should be able to dynamically allocate IPIs > > and use common APIs such as request_irq()/request_nmi() to tell IPI > > specific handlers. > > > > If this approach looks sane to you then I can start working on a PoC > > implementation for arm64. > > I can't say I'm keen. This IPI framework doesn't really work for the > GIC: > > - it requires a separate irqdomain to be able to guarantee that you > allocate the hwirq in the SGI range. What is the point? > - it creates yet another level of indirection on IPI injection > > This framework was created to deal with two cases: > - systems that can't represent their IPI with a single hwirq spanning > all the CPUs > - "accelerator cores" that don't run Linux > > The GIC architecture avoids the first point, and I don't even want to > think of the second one. > > Also, it doesn't solve the initial problem, which is to bootstrap the > whole thing. The IPI framework relies on an irqdomain to be created the > first place. This would mean teaching the arch code about the > intricacies of irqdomains, FW nodes and other terrible things. All > things which are better hidden in the GIC drivers (not to mention the > other horror stories that are the RPi-2/3 irqchip and the Huawei GIC > knock-off). > > What I have in mind is to replace the set_smp_cross_call() with > something that passes the required set of information (interrupt range, > at the very least). The only thing that I plan to reuse from the IPI > framework is the chip->ipi_send_mask() callback. > Fair enough, I will just pass the allocated interrupt range base instead of set_smp_cross_call() and use __ipi_send_mask() to invoke a particular IPI. And to request an arch specific IPI as NMI, will use arch_get_ipinr_nmi() and in turn use request_percpu_nmi() to turn that particular IPI as NMI. Is there anything that I missed here? -Sumit > Thanks, > > M. > -- > Jazz is not dead. It just smells funny...
Hi Marc, On Thu, 30 Apr 2020 at 17:43, Sumit Garg <sumit.garg@linaro.org> wrote: > > On Thu, 30 Apr 2020 at 14:43, Marc Zyngier <maz@kernel.org> wrote: > > > > On Thu, 30 Apr 2020 12:50:28 +0530 > > Sumit Garg <sumit.garg@linaro.org> wrote: > > > > > Hi Marc, > > > > > > On Wed, 29 Apr 2020 at 13:53, Marc Zyngier <maz@kernel.org> wrote: > > > > [...] > > > > > > What I would like is for the arch code to request these interrupts as > > > > normal interrupts, for which there is one problem to solve: how do you > > > > find out about the Linux IRQ number for a given IPI. Or rather, how > > > > do you get rid of the requirement to have IPI numbers at all and just > > > > say "give me a per-cpu interrupt that I can use as an IPI, and by the > > > > way here's the handler you can call". > > > > > > I think what you are looking for here is something that could be > > > sufficed via enabling "CONFIG_GENERIC_IRQ_IPI" framework for arm64/arm > > > architectures. It's currently used for mips architecture. Looking at > > > its implementation, I think it should be possible to hook up SGIs > > > under new IPI irq_domain for GICv2/v3. > > > > > > So with this framework we should be able to dynamically allocate IPIs > > > and use common APIs such as request_irq()/request_nmi() to tell IPI > > > specific handlers. > > > > > > If this approach looks sane to you then I can start working on a PoC > > > implementation for arm64. > > > > I can't say I'm keen. This IPI framework doesn't really work for the > > GIC: > > > > - it requires a separate irqdomain to be able to guarantee that you > > allocate the hwirq in the SGI range. What is the point? > > - it creates yet another level of indirection on IPI injection > > > > This framework was created to deal with two cases: > > - systems that can't represent their IPI with a single hwirq spanning > > all the CPUs > > - "accelerator cores" that don't run Linux > > > > The GIC architecture avoids the first point, and I don't even want to > > think of the second one. > > > > Also, it doesn't solve the initial problem, which is to bootstrap the > > whole thing. The IPI framework relies on an irqdomain to be created the > > first place. This would mean teaching the arch code about the > > intricacies of irqdomains, FW nodes and other terrible things. All > > things which are better hidden in the GIC drivers (not to mention the > > other horror stories that are the RPi-2/3 irqchip and the Huawei GIC > > knock-off). > > > > What I have in mind is to replace the set_smp_cross_call() with > > something that passes the required set of information (interrupt range, > > at the very least). The only thing that I plan to reuse from the IPI > > framework is the chip->ipi_send_mask() callback. > > > > Fair enough, I will just pass the allocated interrupt range base > instead of set_smp_cross_call() and use __ipi_send_mask() to invoke a > particular IPI. Thinking more about this, there seems to be multiple irqchip drivers registering softirq API via set_smp_cross_call(). So we need to introduce a new API instead of replacing set_smp_cross_call() under "CONFIG_GENERIC_IRQ_IPI" macro until all drivers switch to IPIs as full interrupts. BTW, could we take up this generalization as follow-up work as it seems to be independent of current IPI NMI work? > > And to request an arch specific IPI as NMI, will use > arch_get_ipinr_nmi() and in turn use request_percpu_nmi() to turn that > particular IPI as NMI. I have updated the second patch [1] in my tree to incorporate these changes. The updated commit log is as follows: commit 25c96663126264ec758c49a4a01a9c285f4ccc61 Author: Sumit Garg <sumit.garg@linaro.org> Date: Wed Apr 22 16:29:59 2020 +0530 irqchip/gic-v3: Setup arch specific IPI as pseudo NMI Add support to mark arch specific IPI as pseudo NMI. Currently its used to allow arm64 specific IPI_CALL_NMI_FUNC to be marked as pseudo NMI. Brief description of changes: - Update NMI setup/teardown routines for SGIs. - Enable NMI support prior to gic_smp_init(). - Setup custom flow handler for SGI setup as NMI. - Request, prepare and enable arch specific IPI as per CPU NMI using common APIs. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Please have a look and let me know if this is something you were looking for. [1] https://git.linaro.org/people/sumit.garg/linux.git/commit/?h=kgdb-nmi&id=25c96663126264ec758c49a4a01a9c285f4ccc61 -Sumit > > Thanks, > > > > M. > > -- > > Jazz is not dead. It just smells funny...
On Fri, 1 May 2020 at 18:33, Sumit Garg <sumit.garg@linaro.org> wrote: > > Hi Marc, > > On Thu, 30 Apr 2020 at 17:43, Sumit Garg <sumit.garg@linaro.org> wrote: > > > > On Thu, 30 Apr 2020 at 14:43, Marc Zyngier <maz@kernel.org> wrote: > > > > > > On Thu, 30 Apr 2020 12:50:28 +0530 > > > Sumit Garg <sumit.garg@linaro.org> wrote: > > > > > > > Hi Marc, > > > > > > > > On Wed, 29 Apr 2020 at 13:53, Marc Zyngier <maz@kernel.org> wrote: > > > > > > [...] > > > > > > > > What I would like is for the arch code to request these interrupts as > > > > > normal interrupts, for which there is one problem to solve: how do you > > > > > find out about the Linux IRQ number for a given IPI. Or rather, how > > > > > do you get rid of the requirement to have IPI numbers at all and just > > > > > say "give me a per-cpu interrupt that I can use as an IPI, and by the > > > > > way here's the handler you can call". > > > > > > > > I think what you are looking for here is something that could be > > > > sufficed via enabling "CONFIG_GENERIC_IRQ_IPI" framework for arm64/arm > > > > architectures. It's currently used for mips architecture. Looking at > > > > its implementation, I think it should be possible to hook up SGIs > > > > under new IPI irq_domain for GICv2/v3. > > > > > > > > So with this framework we should be able to dynamically allocate IPIs > > > > and use common APIs such as request_irq()/request_nmi() to tell IPI > > > > specific handlers. > > > > > > > > If this approach looks sane to you then I can start working on a PoC > > > > implementation for arm64. > > > > > > I can't say I'm keen. This IPI framework doesn't really work for the > > > GIC: > > > > > > - it requires a separate irqdomain to be able to guarantee that you > > > allocate the hwirq in the SGI range. What is the point? > > > - it creates yet another level of indirection on IPI injection > > > > > > This framework was created to deal with two cases: > > > - systems that can't represent their IPI with a single hwirq spanning > > > all the CPUs > > > - "accelerator cores" that don't run Linux > > > > > > The GIC architecture avoids the first point, and I don't even want to > > > think of the second one. > > > > > > Also, it doesn't solve the initial problem, which is to bootstrap the > > > whole thing. The IPI framework relies on an irqdomain to be created the > > > first place. This would mean teaching the arch code about the > > > intricacies of irqdomains, FW nodes and other terrible things. All > > > things which are better hidden in the GIC drivers (not to mention the > > > other horror stories that are the RPi-2/3 irqchip and the Huawei GIC > > > knock-off). > > > > > > What I have in mind is to replace the set_smp_cross_call() with > > > something that passes the required set of information (interrupt range, > > > at the very least). The only thing that I plan to reuse from the IPI > > > framework is the chip->ipi_send_mask() callback. > > > > > > > Fair enough, I will just pass the allocated interrupt range base > > instead of set_smp_cross_call() and use __ipi_send_mask() to invoke a > > particular IPI. > > Thinking more about this, there seems to be multiple irqchip drivers > registering softirq API via set_smp_cross_call(). So we need to > introduce a new API instead of replacing set_smp_cross_call() under > "CONFIG_GENERIC_IRQ_IPI" macro until all drivers switch to IPIs as > full interrupts. > > BTW, could we take up this generalization as follow-up work as it > seems to be independent of current IPI NMI work? > > > > > And to request an arch specific IPI as NMI, will use > > arch_get_ipinr_nmi() and in turn use request_percpu_nmi() to turn that > > particular IPI as NMI. > > I have updated the second patch [1] in my tree to incorporate these > changes. The updated commit log is as follows: > > commit 25c96663126264ec758c49a4a01a9c285f4ccc61 > Author: Sumit Garg <sumit.garg@linaro.org> > Date: Wed Apr 22 16:29:59 2020 +0530 > > irqchip/gic-v3: Setup arch specific IPI as pseudo NMI > > Add support to mark arch specific IPI as pseudo NMI. Currently its used > to allow arm64 specific IPI_CALL_NMI_FUNC to be marked as pseudo NMI. > > Brief description of changes: > - Update NMI setup/teardown routines for SGIs. > - Enable NMI support prior to gic_smp_init(). > - Setup custom flow handler for SGI setup as NMI. > - Request, prepare and enable arch specific IPI as per CPU NMI using > common APIs. > > Signed-off-by: Sumit Garg <sumit.garg@linaro.org> > > Please have a look and let me know if this is something you were looking for. > In case there are no major objections to this approach, I will post complete v2 patch-set (alongwith Marc's patches) for detailed review. -Sumit > [1] https://git.linaro.org/people/sumit.garg/linux.git/commit/?h=kgdb-nmi&id=25c96663126264ec758c49a4a01a9c285f4ccc61 > > -Sumit > > > > Thanks, > > > > > > M. > > > -- > > > Jazz is not dead. It just smells funny...
On 2020-05-05 05:09, Sumit Garg wrote: > On Fri, 1 May 2020 at 18:33, Sumit Garg <sumit.garg@linaro.org> wrote: [...] > In case there are no major objections to this approach, I will post > complete v2 patch-set (alongwith Marc's patches) for detailed review. As this is still a work in progress (I'm currently wrestling with the stupid RPi driver), whatever you have is unlikely to apply on top of the final series. I'm not going to stop you from posting the patches, it is just that they will be obsolete by the end of the week... Thanks, M.
On Tue, 5 May 2020 at 15:38, Marc Zyngier <maz@kernel.org> wrote: > > On 2020-05-05 05:09, Sumit Garg wrote: > > On Fri, 1 May 2020 at 18:33, Sumit Garg <sumit.garg@linaro.org> wrote: > > [...] > > > In case there are no major objections to this approach, I will post > > complete v2 patch-set (alongwith Marc's patches) for detailed review. > > As this is still a work in progress (I'm currently wrestling with > the stupid RPi driver), whatever you have is unlikely to apply on > top of the final series. > > I'm not going to stop you from posting the patches, it is just that > they will be obsolete by the end of the week... Thanks for the heads up. Will wait for your final series. But while working on an NMI request, I noticed a hack in common gic code [1] which basically enables all SGIs for every CPU by default. This hack is quite similar to mine initial hack to set priority for a particular SGI by default to act as pseudo NMI. Due to this hack I got following error message while configuring SGI as NMI: [ 0.000000] GICv3: Cannot set NMI property of enabled IRQ 8 [ 0.000000] genirq: Failed to setup NMI delivery: irq 8 I think chained IRQs worked for you due to this hack only as it doesn't seem to enable SGIs per CPU. IMO, as we shift to SGIs being standard interrupts, we should also rely on standard interrupt framework to enable SGIs. So it seems the correct way would be to use "request_percpu_irq()" and "enable_percpu_irq()" for configuring SGIs as demonstrated in updated commit here [2]. Also, we should get rid of this hack as demonstrated via commit [3]. Apart from above changes, there was a minor update needed for commit "irqchip/gic-v3: Describe the SGI range" [4]. I hope these updates are useful for you while preparing the final series. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/irqchip/irq-gic-common.c#n155 [2] https://git.linaro.org/people/sumit.garg/linux.git/commit/?h=kgdb-nmi&id=e208979b5165d753d144db57e0cb8646fdedc495 [3] https://git.linaro.org/people/sumit.garg/linux.git/commit/?h=kgdb-nmi&id=cd6d0d7cea14ac16156f0dbd297940df382f8cea [4] https://git.linaro.org/people/sumit.garg/linux.git/commit/?h=kgdb-nmi&id=1180e9c54547ec05d96cc6b36c26005059c90d9a -Sumit > > Thanks, > > M. > -- > Jazz is not dead. It just smells funny...
Hi Marc, On Tue, 5 May 2020 at 17:03, Sumit Garg <sumit.garg@linaro.org> wrote: > > On Tue, 5 May 2020 at 15:38, Marc Zyngier <maz@kernel.org> wrote: > > > > On 2020-05-05 05:09, Sumit Garg wrote: > > > On Fri, 1 May 2020 at 18:33, Sumit Garg <sumit.garg@linaro.org> wrote: > > > > [...] > > > > > In case there are no major objections to this approach, I will post > > > complete v2 patch-set (alongwith Marc's patches) for detailed review. > > > > As this is still a work in progress (I'm currently wrestling with > > the stupid RPi driver), whatever you have is unlikely to apply on > > top of the final series. > > > > I'm not going to stop you from posting the patches, it is just that > > they will be obsolete by the end of the week... > > Thanks for the heads up. Will wait for your final series. > Were you able to give a final shape to your SGIs related patch-set? -Sumit > But while working on an NMI request, I noticed a hack in common gic > code [1] which basically enables all SGIs for every CPU by default. > This hack is quite similar to mine initial hack to set priority for a > particular SGI by default to act as pseudo NMI. > > Due to this hack I got following error message while configuring SGI as NMI: > > [ 0.000000] GICv3: Cannot set NMI property of enabled IRQ 8 > [ 0.000000] genirq: Failed to setup NMI delivery: irq 8 > > I think chained IRQs worked for you due to this hack only as it > doesn't seem to enable SGIs per CPU. > > IMO, as we shift to SGIs being standard interrupts, we should also > rely on standard interrupt framework to enable SGIs. So it seems the > correct way would be to use "request_percpu_irq()" and > "enable_percpu_irq()" for configuring SGIs as demonstrated in updated > commit here [2]. > > Also, we should get rid of this hack as demonstrated via commit [3]. > > Apart from above changes, there was a minor update needed for commit > "irqchip/gic-v3: Describe the SGI range" [4]. > > I hope these updates are useful for you while preparing the final series. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/irqchip/irq-gic-common.c#n155 > [2] https://git.linaro.org/people/sumit.garg/linux.git/commit/?h=kgdb-nmi&id=e208979b5165d753d144db57e0cb8646fdedc495 > [3] https://git.linaro.org/people/sumit.garg/linux.git/commit/?h=kgdb-nmi&id=cd6d0d7cea14ac16156f0dbd297940df382f8cea > [4] https://git.linaro.org/people/sumit.garg/linux.git/commit/?h=kgdb-nmi&id=1180e9c54547ec05d96cc6b36c26005059c90d9a > > -Sumit > > > > > Thanks, > > > > M. > > -- > > Jazz is not dead. It just smells funny...
On 2020-05-13 11:02, Sumit Garg wrote: > Hi Marc, > > On Tue, 5 May 2020 at 17:03, Sumit Garg <sumit.garg@linaro.org> wrote: >> >> On Tue, 5 May 2020 at 15:38, Marc Zyngier <maz@kernel.org> wrote: >> > >> > On 2020-05-05 05:09, Sumit Garg wrote: >> > > On Fri, 1 May 2020 at 18:33, Sumit Garg <sumit.garg@linaro.org> wrote: >> > >> > [...] >> > >> > > In case there are no major objections to this approach, I will post >> > > complete v2 patch-set (alongwith Marc's patches) for detailed review. >> > >> > As this is still a work in progress (I'm currently wrestling with >> > the stupid RPi driver), whatever you have is unlikely to apply on >> > top of the final series. >> > >> > I'm not going to stop you from posting the patches, it is just that >> > they will be obsolete by the end of the week... >> >> Thanks for the heads up. Will wait for your final series. >> > > Were you able to give a final shape to your SGIs related patch-set? See https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=irq/ipi-as-irq Thanks, M.
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index d7006ef..be361bf 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -609,17 +609,29 @@ static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) if (irqs_enabled) nmi_enter(); - if (static_branch_likely(&supports_deactivate_key)) - gic_write_eoir(irqnr); /* * Leave the PSR.I bit set to prevent other NMIs to be * received while handling this one. * PSR.I will be restored when we ERET to the * interrupted context. */ - err = handle_domain_nmi(gic_data.domain, irqnr, regs); - if (err) - gic_deactivate_unhandled(irqnr); + if (likely(irqnr > 15)) { + if (static_branch_likely(&supports_deactivate_key)) + gic_write_eoir(irqnr); + + err = handle_domain_nmi(gic_data.domain, irqnr, regs); + if (err) + gic_deactivate_unhandled(irqnr); + } else { + gic_write_eoir(irqnr); + if (static_branch_likely(&supports_deactivate_key)) + gic_write_dir(irqnr); +#ifdef CONFIG_SMP + handle_IPI(irqnr, regs); +#else + WARN_ONCE(true, "Unexpected SGI received!\n"); +#endif + } if (irqs_enabled) nmi_exit();
With pseudo NMIs enabled, interrupt controller can be configured to deliver SGI as a pseudo NMI. So add corresponding handling for SGIs. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> --- drivers/irqchip/irq-gic-v3.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-)