| Message ID | 20200427163238.1.Ib1faaabe236e37ea73be9b8dcc6aa034cb3c8804@changeid (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 6eefaee4f2d366a389da0eb95e524ba82bf358c4 |
| Headers | show |
| Series | spi: pxa2xx: Apply CS clk quirk to BXT | expand |
On Mon, 27 Apr 2020 16:32:48 -0700, Evan Green wrote: > With a couple allies at Intel, and much badgering, I got confirmation > from Intel that at least BXT suffers from the same SPI chip-select > issue as Cannonlake (and beyond). The issue being that after going > through runtime suspend/resume, toggling the chip-select line without > also sending data does nothing. > > Add the quirk to BXT to briefly toggle dynamic clock gating off and > on, forcing the fabric to wake up enough to notice the CS register > change. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.8 Thanks! [1/1] spi: pxa2xx: Apply CS clk quirk to BXT commit: 6eefaee4f2d366a389da0eb95e524ba82bf358c4 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 73d2a65d0b6ef..20dcbd35611a7 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -150,6 +150,7 @@ static const struct lpss_config lpss_platforms[] = { .tx_threshold_hi = 48, .cs_sel_shift = 8, .cs_sel_mask = 3 << 8, + .cs_clk_stays_gated = true, }, { /* LPSS_CNL_SSP */ .offset = 0x200,
With a couple allies at Intel, and much badgering, I got confirmation from Intel that at least BXT suffers from the same SPI chip-select issue as Cannonlake (and beyond). The issue being that after going through runtime suspend/resume, toggling the chip-select line without also sending data does nothing. Add the quirk to BXT to briefly toggle dynamic clock gating off and on, forcing the fabric to wake up enough to notice the CS register change. Signed-off-by: Evan Green <evgreen@chromium.org> Cc: Shobhit Srivastava <shobhit.srivastava@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> --- I don't actually have a BXT (Broxton/Apollolake?) system to test this. To be honest I suspect the issue is there in older generations as well, but I couldn't get Intel to confirm that, so this seemed like the only safe change. --- drivers/spi/spi-pxa2xx.c | 1 + 1 file changed, 1 insertion(+)