diff mbox series

[25/40] rtw88: 8723d: Add LC calibration

Message ID 20200417074653.15591-26-yhchuang@realtek.com (mailing list archive)
State Changes Requested
Delegated to: Kalle Valo
Headers show
Series rtw88: add support for 802.11n RTL8723DE devices | expand

Commit Message

Tony Chuang April 17, 2020, 7:46 a.m. UTC 
From: Ping-Ke Shih <pkshih@realtek.com>

LC calibration is done by hardware circuit. Driver sets the LCK bit to kick
start, and then poll the bit to check if it's done.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com>
---
 drivers/net/wireless/realtek/rtw88/rtw8723d.c | 30 +++++++++++++++++++
 drivers/net/wireless/realtek/rtw88/rtw8723d.h |  2 ++
 2 files changed, 32 insertions(+)

Comments

Sebastian Andrzej Siewior April 30, 2020, 1:57 p.m. UTC | #1 
On 2020-04-17 15:46:38 [+0800], yhchuang@realtek.com wrote:
> index cf897af380c1..94784c7f0743 100644
> --- a/drivers/net/wireless/realtek/rtw88/rtw8723d.c
> +++ b/drivers/net/wireless/realtek/rtw88/rtw8723d.c
> @@ -64,6 +64,33 @@ static const struct rtw_hw_reg rtw8723d_txagc[] = {
>  #define WLAN_LTR_CTRL1		0xCB004010
>  #define WLAN_LTR_CTRL2		0x01233425
>  
> +static void rtw8723d_lck(struct rtw_dev *rtwdev)
> +{
> +#define BIT_LCK		BIT(15)

please don't add defines like this within a function.

> +	u8 val_ctx;
> +	u32 lc_cal, cnt;
> +
> +	val_ctx = rtw_read8(rtwdev, REG_CTX);
> +	if ((val_ctx & BIT_MASK_CTX_TYPE) != 0)
> +		rtw_write8(rtwdev, REG_CTX, val_ctx & ~BIT_MASK_CTX_TYPE);
> +	else
> +		rtw_write8(rtwdev, REG_TXPAUSE, 0xFF);
> +	lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
> +
> +	rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal | BIT_LCK);
> +	for (cnt = 0; cnt < 100; cnt++) {
> +		if (rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, BIT_LCK) != 0x1)
> +			break;
> +		mdelay(10);

Do you have any numbers on how long this takes? Like best-case, on average,
worst case? I'm asking because if the bit does not flip on the first
read then you busy-loop-delay here for 10ms. If it does not flip at all,
you busy waited a whole second without any consequence. 

It looks like this context here is not atomic so msleep() would work where.

Sebastian
Tony Chuang May 4, 2020, 8:40 a.m. UTC | #2 
> On 2020-04-17 15:46:38 [+0800], yhchuang@realtek.com wrote:
> > index cf897af380c1..94784c7f0743 100644
> > --- a/drivers/net/wireless/realtek/rtw88/rtw8723d.c
> > +++ b/drivers/net/wireless/realtek/rtw88/rtw8723d.c
> > @@ -64,6 +64,33 @@ static const struct rtw_hw_reg rtw8723d_txagc[] = {
> >  #define WLAN_LTR_CTRL1		0xCB004010
> >  #define WLAN_LTR_CTRL2		0x01233425
> >
> > +static void rtw8723d_lck(struct rtw_dev *rtwdev)
> > +{
> > +#define BIT_LCK		BIT(15)
> 
> please don't add defines like this within a function.
> 
> > +	u8 val_ctx;
> > +	u32 lc_cal, cnt;
> > +
> > +	val_ctx = rtw_read8(rtwdev, REG_CTX);
> > +	if ((val_ctx & BIT_MASK_CTX_TYPE) != 0)
> > +		rtw_write8(rtwdev, REG_CTX, val_ctx & ~BIT_MASK_CTX_TYPE);
> > +	else
> > +		rtw_write8(rtwdev, REG_TXPAUSE, 0xFF);
> > +	lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
> > +
> > +	rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal |
> BIT_LCK);
> > +	for (cnt = 0; cnt < 100; cnt++) {
> > +		if (rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, BIT_LCK) != 0x1)
> > +			break;
> > +		mdelay(10);
> 
> Do you have any numbers on how long this takes? Like best-case, on average,
> worst case? I'm asking because if the bit does not flip on the first
> read then you busy-loop-delay here for 10ms. If it does not flip at all,
> you busy waited a whole second without any consequence.
> 
> It looks like this context here is not atomic so msleep() would work where.

Indeed, I think read_poll_timeout() will be good for this case. Thanks.

> 
> Sebastian
> 

Yen-Hsuan
diff mbox series

Patch

diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723d.c b/drivers/net/wireless/realtek/rtw88/rtw8723d.c
index cf897af380c1..94784c7f0743 100644
--- a/drivers/net/wireless/realtek/rtw88/rtw8723d.c
+++ b/drivers/net/wireless/realtek/rtw88/rtw8723d.c
@@ -64,6 +64,33 @@  static const struct rtw_hw_reg rtw8723d_txagc[] = {
 #define WLAN_LTR_CTRL1		0xCB004010
 #define WLAN_LTR_CTRL2		0x01233425
 
+static void rtw8723d_lck(struct rtw_dev *rtwdev)
+{
+#define BIT_LCK		BIT(15)
+	u8 val_ctx;
+	u32 lc_cal, cnt;
+
+	val_ctx = rtw_read8(rtwdev, REG_CTX);
+	if ((val_ctx & BIT_MASK_CTX_TYPE) != 0)
+		rtw_write8(rtwdev, REG_CTX, val_ctx & ~BIT_MASK_CTX_TYPE);
+	else
+		rtw_write8(rtwdev, REG_TXPAUSE, 0xFF);
+	lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
+
+	rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal | BIT_LCK);
+	for (cnt = 0; cnt < 100; cnt++) {
+		if (rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, BIT_LCK) != 0x1)
+			break;
+		mdelay(10);
+	}
+
+	rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal);
+	if ((val_ctx & BIT_MASK_CTX_TYPE) != 0)
+		rtw_write8(rtwdev, REG_CTX, val_ctx);
+	else
+		rtw_write8(rtwdev, REG_TXPAUSE, 0x00);
+}
+
 static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev)
 {
 	u8 xtal_cap;
@@ -125,6 +152,9 @@  static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev)
 	rtw_phy_init(rtwdev);
 
 	rtw_write16_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN);
+
+	rtw8723d_lck(rtwdev);
+
 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);
 }
diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723d.h b/drivers/net/wireless/realtek/rtw88/rtw8723d.h
index b5b7fc9cd1c8..64a1f2359c23 100644
--- a/drivers/net/wireless/realtek/rtw88/rtw8723d.h
+++ b/drivers/net/wireless/realtek/rtw88/rtw8723d.h
@@ -97,6 +97,8 @@  struct rtw8723d_efuse {
 #define REG_OFDM_FA_RSTD_11N	0x0d00
 #define BIT_MASK_OFDM_FA_RST1	BIT(27)
 #define BIT_MASK_OFDM_FA_KEEP1	BIT(31)
+#define REG_CTX			0x0d03
+#define BIT_MASK_CTX_TYPE	GENMASK(6, 4)
 #define REG_OFDM1_CFOTRK	0x0d2c
 #define REG_OFDM1_CSI1		0x0d40
 #define REG_OFDM1_CSI2		0x0d44