| Message ID | 20200504131326.18290-2-broonie@kernel.org (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | bd507ca2773b20f554a3e14f7aa9080e45ee399a |
| Headers | show |
| Series | arm64: Make NOP handling a whitelist | expand |
On Mon, May 04, 2020 at 02:13:23PM +0100, Mark Brown wrote: > Add constants for decoding newer instructions defined in the HINT space. > Since we are now decoding both the op2 and CRm fields rename the enum as > well; this is compatible with what the existing users are doing. > > Signed-off-by: Mark Brown <broonie@kernel.org> > Acked-by: Catalin Marinas <catalin.marinas@arm.com> These all look correct to me per the "Architectural hint instructions" table on page C5-378 of ARM DDI 0487F.a, so: Acked-by: Mark Rutland <mark.rutland@arm.com> It looks like DGH was added recently, so we might want to follow up with that at some point, but it's certianly not necessary now. Mark. > --- > arch/arm64/include/asm/insn.h | 28 ++++++++++++++++++++++++++-- > arch/arm64/kernel/insn.c | 2 +- > 2 files changed, 27 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h > index bb313dde58a4..575675145fe2 100644 > --- a/arch/arm64/include/asm/insn.h > +++ b/arch/arm64/include/asm/insn.h > @@ -39,13 +39,37 @@ enum aarch64_insn_encoding_class { > * system instructions */ > }; > > -enum aarch64_insn_hint_op { > +enum aarch64_insn_hint_cr_op { > AARCH64_INSN_HINT_NOP = 0x0 << 5, > AARCH64_INSN_HINT_YIELD = 0x1 << 5, > AARCH64_INSN_HINT_WFE = 0x2 << 5, > AARCH64_INSN_HINT_WFI = 0x3 << 5, > AARCH64_INSN_HINT_SEV = 0x4 << 5, > AARCH64_INSN_HINT_SEVL = 0x5 << 5, > + > + AARCH64_INSN_HINT_XPACLRI = 0x07 << 5, > + AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5, > + AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5, > + AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5, > + AARCH64_INSN_HINT_AUTIB_1716 = 0x0E << 5, > + AARCH64_INSN_HINT_PACIAZ = 0x18 << 5, > + AARCH64_INSN_HINT_PACIASP = 0x19 << 5, > + AARCH64_INSN_HINT_PACIBZ = 0x1A << 5, > + AARCH64_INSN_HINT_PACIBSP = 0x1B << 5, > + AARCH64_INSN_HINT_AUTIAZ = 0x1C << 5, > + AARCH64_INSN_HINT_AUTIASP = 0x1D << 5, > + AARCH64_INSN_HINT_AUTIBZ = 0x1E << 5, > + AARCH64_INSN_HINT_AUTIBSP = 0x1F << 5, > + > + AARCH64_INSN_HINT_ESB = 0x10 << 5, > + AARCH64_INSN_HINT_PSB = 0x11 << 5, > + AARCH64_INSN_HINT_TSB = 0x12 << 5, > + AARCH64_INSN_HINT_CSDB = 0x14 << 5, > + > + AARCH64_INSN_HINT_BTI = 0x20 << 5, > + AARCH64_INSN_HINT_BTIC = 0x22 << 5, > + AARCH64_INSN_HINT_BTIJ = 0x24 << 5, > + AARCH64_INSN_HINT_BTIJC = 0x26 << 5, > }; > > enum aarch64_insn_imm_type { > @@ -370,7 +394,7 @@ u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr, > enum aarch64_insn_branch_type type); > u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr, > enum aarch64_insn_condition cond); > -u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op); > +u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op); > u32 aarch64_insn_gen_nop(void); > u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg, > enum aarch64_insn_branch_type type); > diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c > index 4a9e773a177f..d63d9cd8b4a2 100644 > --- a/arch/arm64/kernel/insn.c > +++ b/arch/arm64/kernel/insn.c > @@ -574,7 +574,7 @@ u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr, > offset >> 2); > } > > -u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op) > +u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op) > { > return aarch64_insn_get_hint_value() | op; > } > -- > 2.20.1 >
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index bb313dde58a4..575675145fe2 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -39,13 +39,37 @@ enum aarch64_insn_encoding_class { * system instructions */ }; -enum aarch64_insn_hint_op { +enum aarch64_insn_hint_cr_op { AARCH64_INSN_HINT_NOP = 0x0 << 5, AARCH64_INSN_HINT_YIELD = 0x1 << 5, AARCH64_INSN_HINT_WFE = 0x2 << 5, AARCH64_INSN_HINT_WFI = 0x3 << 5, AARCH64_INSN_HINT_SEV = 0x4 << 5, AARCH64_INSN_HINT_SEVL = 0x5 << 5, + + AARCH64_INSN_HINT_XPACLRI = 0x07 << 5, + AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5, + AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5, + AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5, + AARCH64_INSN_HINT_AUTIB_1716 = 0x0E << 5, + AARCH64_INSN_HINT_PACIAZ = 0x18 << 5, + AARCH64_INSN_HINT_PACIASP = 0x19 << 5, + AARCH64_INSN_HINT_PACIBZ = 0x1A << 5, + AARCH64_INSN_HINT_PACIBSP = 0x1B << 5, + AARCH64_INSN_HINT_AUTIAZ = 0x1C << 5, + AARCH64_INSN_HINT_AUTIASP = 0x1D << 5, + AARCH64_INSN_HINT_AUTIBZ = 0x1E << 5, + AARCH64_INSN_HINT_AUTIBSP = 0x1F << 5, + + AARCH64_INSN_HINT_ESB = 0x10 << 5, + AARCH64_INSN_HINT_PSB = 0x11 << 5, + AARCH64_INSN_HINT_TSB = 0x12 << 5, + AARCH64_INSN_HINT_CSDB = 0x14 << 5, + + AARCH64_INSN_HINT_BTI = 0x20 << 5, + AARCH64_INSN_HINT_BTIC = 0x22 << 5, + AARCH64_INSN_HINT_BTIJ = 0x24 << 5, + AARCH64_INSN_HINT_BTIJC = 0x26 << 5, }; enum aarch64_insn_imm_type { @@ -370,7 +394,7 @@ u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr, enum aarch64_insn_branch_type type); u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr, enum aarch64_insn_condition cond); -u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op); +u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op); u32 aarch64_insn_gen_nop(void); u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg, enum aarch64_insn_branch_type type); diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index 4a9e773a177f..d63d9cd8b4a2 100644 --- a/arch/arm64/kernel/insn.c +++ b/arch/arm64/kernel/insn.c @@ -574,7 +574,7 @@ u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr, offset >> 2); } -u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_op op) +u32 __kprobes aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op) { return aarch64_insn_get_hint_value() | op; }