| Message ID | 1588500367-1056-8-git-send-email-chenhc@lemote.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: MIPS: Add Loongson-3 support (Host Side) | expand |
нед, 3. мај 2020. у 12:12 Huacai Chen <chenhc@lemote.com> је написао/ла: > > KVM guest has two levels of address translation: guest tlb translates > GVA to GPA, and root tlb translates GPA to HPA. By default guest's CCA > is controlled by guest tlb, but Loongson-3 maintains all cache coherency > by hardware (including multi-core coherency and I/O DMA coherency) so it > prefers all guest mappings be cacheable mappings. Thus, we use root tlb > to control guest's CCA for Loongson-3. > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > arch/mips/kvm/vz.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c > index 422cd06..f9fbbc16 100644 > --- a/arch/mips/kvm/vz.c > +++ b/arch/mips/kvm/vz.c > @@ -2871,6 +2871,12 @@ static int kvm_vz_hardware_enable(void) > if (cpu_has_guestctl2) > clear_c0_guestctl2(0x3f << 10); > > +#ifdef CONFIG_CPU_LOONGSON64 > + /* Control guest CCA attribute */ > + if (cpu_has_csr()) > + csr_writel(csr_readl(0xffffffec) | 0x1, 0xffffffec); > +#endif > + > return 0; > } > > -- > 2.7.0 > Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c index 422cd06..f9fbbc16 100644 --- a/arch/mips/kvm/vz.c +++ b/arch/mips/kvm/vz.c @@ -2871,6 +2871,12 @@ static int kvm_vz_hardware_enable(void) if (cpu_has_guestctl2) clear_c0_guestctl2(0x3f << 10); +#ifdef CONFIG_CPU_LOONGSON64 + /* Control guest CCA attribute */ + if (cpu_has_csr()) + csr_writel(csr_readl(0xffffffec) | 0x1, 0xffffffec); +#endif + return 0; }
KVM guest has two levels of address translation: guest tlb translates GVA to GPA, and root tlb translates GPA to HPA. By default guest's CCA is controlled by guest tlb, but Loongson-3 maintains all cache coherency by hardware (including multi-core coherency and I/O DMA coherency) so it prefers all guest mappings be cacheable mappings. Thus, we use root tlb to control guest's CCA for Loongson-3. Signed-off-by: Huacai Chen <chenhc@lemote.com> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- arch/mips/kvm/vz.c | 6 ++++++ 1 file changed, 6 insertions(+)