| Message ID | 20200511125713.13536-2-qiangqing.zhang@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | perf/imx_ddr: Add system PMU support | expand |
On 11/05/2020 13:57, Joakim Zhang wrote: > The DDR Perf for i.MX8 is a system PMU whose axi id would different from > SoC to SoC. Need expose system PMU identifier for userspace which refer > to /sys/bus/event_source/devices/<PMU DEVICE>/identifier. > > Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> I think that you should have cc'ed DT maintainers/list for this series because of the dt parts. I am not sure on any policy of removing compat string support (in latter patches). Apart from that: Reviewed-by: John Garry <john.garry@huawei.com> > --- > drivers/perf/fsl_imx8_ddr_perf.c | 45 +++++++++++++++++++++++++++++--- > 1 file changed, 42 insertions(+), 3 deletions(-) > > diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c > index 95dca2cb5265..88addbffbbd0 100644 > --- a/drivers/perf/fsl_imx8_ddr_perf.c > +++ b/drivers/perf/fsl_imx8_ddr_perf.c > @@ -50,21 +50,38 @@ static DEFINE_IDA(ddr_ida); > > struct fsl_ddr_devtype_data { > unsigned int quirks; /* quirks needed for different DDR Perf core */ > + const char *identifier; /* system PMU identifier for userspace */ > }; > > -static const struct fsl_ddr_devtype_data imx8_devtype_data; > +static const struct fsl_ddr_devtype_data imx8_devtype_data = { > + .identifier = "i.MX8", > +}; > + > +static const struct fsl_ddr_devtype_data imx8mq_devtype_data = { > + .quirks = DDR_CAP_AXI_ID_FILTER, > + .identifier = "i.MX8MQ", > +}; > + > +static const struct fsl_ddr_devtype_data imx8mm_devtype_data = { > + .quirks = DDR_CAP_AXI_ID_FILTER, > + .identifier = "i.MX8MM", > +}; > > -static const struct fsl_ddr_devtype_data imx8m_devtype_data = { > +static const struct fsl_ddr_devtype_data imx8mn_devtype_data = { > .quirks = DDR_CAP_AXI_ID_FILTER, > + .identifier = "i.MX8MN", > }; > > static const struct fsl_ddr_devtype_data imx8mp_devtype_data = { > .quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED, > + .identifier = "i.MX8MP", > }; > > static const struct of_device_id imx_ddr_pmu_dt_ids[] = { > { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data}, > - { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data}, > + { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data}, > + { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data}, > + { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data}, > { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data}, > { /* sentinel */ } > }; > @@ -84,6 +101,27 @@ struct ddr_pmu { > int id; > }; > > +static ssize_t ddr_perf_identifier_show(struct device *dev, > + struct device_attribute *attr, > + char *page) > +{ > + struct ddr_pmu *pmu = dev_get_drvdata(dev); > + > + return sprintf(page, "%s\n", pmu->devtype_data->identifier); > +} > + > +static struct device_attribute ddr_perf_identifier_attr = > + __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL); > + > +static struct attribute *ddr_perf_identifier_attrs[] = { > + &ddr_perf_identifier_attr.attr, > + NULL, nit: no need for ',' on sentinel > +}; > + > +static struct attribute_group ddr_perf_identifier_attr_group = { > + .attrs = ddr_perf_identifier_attrs, > +}; > + > enum ddr_perf_filter_capabilities { > PERF_CAP_AXI_ID_FILTER = 0, > PERF_CAP_AXI_ID_FILTER_ENHANCED, > @@ -237,6 +275,7 @@ static const struct attribute_group *attr_groups[] = { > &ddr_perf_format_attr_group, > &ddr_perf_cpumask_attr_group, > &ddr_perf_filter_cap_attr_group, > + &ddr_perf_identifier_attr_group, > NULL, > }; > >
diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 95dca2cb5265..88addbffbbd0 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -50,21 +50,38 @@ static DEFINE_IDA(ddr_ida); struct fsl_ddr_devtype_data { unsigned int quirks; /* quirks needed for different DDR Perf core */ + const char *identifier; /* system PMU identifier for userspace */ }; -static const struct fsl_ddr_devtype_data imx8_devtype_data; +static const struct fsl_ddr_devtype_data imx8_devtype_data = { + .identifier = "i.MX8", +}; + +static const struct fsl_ddr_devtype_data imx8mq_devtype_data = { + .quirks = DDR_CAP_AXI_ID_FILTER, + .identifier = "i.MX8MQ", +}; + +static const struct fsl_ddr_devtype_data imx8mm_devtype_data = { + .quirks = DDR_CAP_AXI_ID_FILTER, + .identifier = "i.MX8MM", +}; -static const struct fsl_ddr_devtype_data imx8m_devtype_data = { +static const struct fsl_ddr_devtype_data imx8mn_devtype_data = { .quirks = DDR_CAP_AXI_ID_FILTER, + .identifier = "i.MX8MN", }; static const struct fsl_ddr_devtype_data imx8mp_devtype_data = { .quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED, + .identifier = "i.MX8MP", }; static const struct of_device_id imx_ddr_pmu_dt_ids[] = { { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data}, - { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data}, + { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data}, + { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data}, + { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data}, { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data}, { /* sentinel */ } }; @@ -84,6 +101,27 @@ struct ddr_pmu { int id; }; +static ssize_t ddr_perf_identifier_show(struct device *dev, + struct device_attribute *attr, + char *page) +{ + struct ddr_pmu *pmu = dev_get_drvdata(dev); + + return sprintf(page, "%s\n", pmu->devtype_data->identifier); +} + +static struct device_attribute ddr_perf_identifier_attr = + __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL); + +static struct attribute *ddr_perf_identifier_attrs[] = { + &ddr_perf_identifier_attr.attr, + NULL, +}; + +static struct attribute_group ddr_perf_identifier_attr_group = { + .attrs = ddr_perf_identifier_attrs, +}; + enum ddr_perf_filter_capabilities { PERF_CAP_AXI_ID_FILTER = 0, PERF_CAP_AXI_ID_FILTER_ENHANCED, @@ -237,6 +275,7 @@ static const struct attribute_group *attr_groups[] = { &ddr_perf_format_attr_group, &ddr_perf_cpumask_attr_group, &ddr_perf_filter_cap_attr_group, + &ddr_perf_identifier_attr_group, NULL, };
The DDR Perf for i.MX8 is a system PMU whose axi id would different from SoC to SoC. Need expose system PMU identifier for userspace which refer to /sys/bus/event_source/devices/<PMU DEVICE>/identifier. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> --- drivers/perf/fsl_imx8_ddr_perf.c | 45 +++++++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 3 deletions(-)