Message ID | 20200519030036.1785-2-zhang.lyra@gmail.com (mailing list archive) |
---|---|
State | Accepted, archived |
Headers | show |
Series | [1/2] clk: sprd: mark the local clock symbols static | expand |
On Tue, May 19, 2020 at 11:00 AM Chunyan Zhang <zhang.lyra@gmail.com> wrote: > > From: Chunyan Zhang <chunyan.zhang@unisoc.com> > > The function _sprd_pll_recalc_rate() defines return value to unsigned > long, but it would return a negative value when malloc fail, changing > to return its parent_rate makes more sense, since if the callback > .recalc_rate() is not set, the framework returns the parent_rate as > well. > > Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support") > Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Looks good to me. Reviewed-by: Baolin Wang <baolin.wang7@gmail.com>
Quoting Chunyan Zhang (2020-05-18 20:00:36) > From: Chunyan Zhang <chunyan.zhang@unisoc.com> > > The function _sprd_pll_recalc_rate() defines return value to unsigned > long, but it would return a negative value when malloc fail, changing > to return its parent_rate makes more sense, since if the callback > .recalc_rate() is not set, the framework returns the parent_rate as > well. > > Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support") > Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> > --- Applied to clk-next
diff --git a/drivers/clk/sprd/pll.c b/drivers/clk/sprd/pll.c index 15791484388f..13a322b2535a 100644 --- a/drivers/clk/sprd/pll.c +++ b/drivers/clk/sprd/pll.c @@ -106,7 +106,7 @@ static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll, cfg = kcalloc(regs_num, sizeof(*cfg), GFP_KERNEL); if (!cfg) - return -ENOMEM; + return parent_rate; for (i = 0; i < regs_num; i++) cfg[i] = sprd_pll_read(pll, i);