| Message ID | 20200423135656.2712-4-yezhenyu2@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: tlb: add support for TTL feature | expand |
On Thu, Apr 23, 2020 at 09:56:53PM +0800, Zhenyu Ye wrote: > @@ -190,8 +196,8 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma, > unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm)); > > dsb(ishst); > - __tlbi(vale1is, addr); > - __tlbi_user(vale1is, addr); > + __tlbi_level(vale1is, addr, 0); > + __tlbi_user_level(vale1is, addr, 0); > } This one remains with a level 0 throughout the series. Is this intentional? If we can't guarantee the level here, better to use the non-level __tlbi().
On 2020/5/22 23:49, Catalin Marinas wrote: > On Thu, Apr 23, 2020 at 09:56:53PM +0800, Zhenyu Ye wrote: >> @@ -190,8 +196,8 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma, >> unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm)); >> >> dsb(ishst); >> - __tlbi(vale1is, addr); >> - __tlbi_user(vale1is, addr); >> + __tlbi_level(vale1is, addr, 0); >> + __tlbi_user_level(vale1is, addr, 0); >> } > > This one remains with a level 0 throughout the series. Is this > intentional? If we can't guarantee the level here, better to use the > non-level __tlbi(). > OK, I will change it back to non-level __tlbi(). Thanks, Zhenyu
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 5f9f189bc6d2..892f33235dc7 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -89,6 +89,12 @@ __tlbi(op, arg); \ } while (0) +#define __tlbi_user_level(op, arg, level) do { \ + if (arm64_kernel_unmapped_at_el0()) \ + __tlbi_level(op, (arg | USER_ASID_FLAG), level); \ +} while (0) + + /* * TLB Invalidation * ================ @@ -190,8 +196,8 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma, unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm)); dsb(ishst); - __tlbi(vale1is, addr); - __tlbi_user(vale1is, addr); + __tlbi_level(vale1is, addr, 0); + __tlbi_user_level(vale1is, addr, 0); } static inline void flush_tlb_page(struct vm_area_struct *vma, @@ -231,11 +237,11 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, dsb(ishst); for (addr = start; addr < end; addr += stride) { if (last_level) { - __tlbi(vale1is, addr); - __tlbi_user(vale1is, addr); + __tlbi_level(vale1is, addr, 0); + __tlbi_user_level(vale1is, addr, 0); } else { - __tlbi(vae1is, addr); - __tlbi_user(vae1is, addr); + __tlbi_level(vae1is, addr, 0); + __tlbi_user_level(vae1is, addr, 0); } } dsb(ish);
Add a level-hinted parameter to __tlbi_user, which only gets used if ARMv8.4-TTL gets detected. This patch set the default level value to 0. Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com> --- arch/arm64/include/asm/tlbflush.h | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-)