| Message ID | 20200526094852.6967-1-stanislav.lisovskiy@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1] drm/i915: Fix wrong CDCLK adjustment changes | expand |
On Tue, May 26, 2020 at 12:48:52PM +0300, Stanislav Lisovskiy wrote: > Previous patch didn't take into account all pipes > but only those in state, which could cause wrong > CDCLK conclcusions and calculations. > Also there was a severe issue with min_cdclk being > assigned to 0 every compare cycle. > > Too bad this was found by me only after merge. > This could be also causing the issues in test, however > not clear - anyway marking this as fixing the > "Adjust CDCLK accordingly to our DBuf bw needs". > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > Fixes: cd1915460861 ("Adjust CDCLK accordingly to our DBuf bw needs") > --- > drivers/gpu/drm/i915/display/intel_bw.c | 51 ++++++++++++-------- > drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +++++--- > drivers/gpu/drm/i915/display/intel_display.c | 26 +++++----- > 3 files changed, 53 insertions(+), 43 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > index a79bd7aeb03b..8096138abecc 100644 > --- a/drivers/gpu/drm/i915/display/intel_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > @@ -437,6 +437,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > struct intel_crtc *crtc; > int max_bw = 0; > int slice_id; > + enum pipe pipe; > int i; > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > @@ -447,7 +448,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > if (IS_ERR(new_bw_state)) > return PTR_ERR(new_bw_state); > > - crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe]; > + old_bw_state = intel_atomic_get_old_bw_state(state); > + > + crtc_bw = &new_bw_state->dbuf_bw[pipe]; > > memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); > > @@ -478,6 +481,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) > crtc_bw->used_bw[slice_id] += data_rate; > } > + } > + > + if (!old_bw_state) > + return 0; > + > + for_each_pipe(dev_priv, pipe) { > + struct intel_dbuf_bw *crtc_bw; > + So the condition !old_bw_state() will make sure we loop through only the active pipes and compute crtc_bw only for those right? Manasi > + crtc_bw = &new_bw_state->dbuf_bw[pipe]; > > for_each_dbuf_slice(slice_id) { > /* > @@ -490,14 +502,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > */ > max_bw += crtc_bw->used_bw[slice_id]; > } > - > - new_bw_state->min_cdclk = max_bw / 64; > - > - old_bw_state = intel_atomic_get_old_bw_state(state); > } > > - if (!old_bw_state) > - return 0; > + new_bw_state->min_cdclk = max_bw / 64; > > if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > int ret = intel_atomic_lock_global_state(&new_bw_state->base); > @@ -511,34 +518,38 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > int intel_bw_calc_min_cdclk(struct intel_atomic_state *state) > { > - int i; > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > + struct intel_bw_state *new_bw_state = NULL; > + struct intel_bw_state *old_bw_state = NULL; > const struct intel_crtc_state *crtc_state; > struct intel_crtc *crtc; > int min_cdclk = 0; > - struct intel_bw_state *new_bw_state = NULL; > - struct intel_bw_state *old_bw_state = NULL; > + enum pipe pipe; > + int i; > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > - struct intel_cdclk_state *cdclk_state; > - > new_bw_state = intel_atomic_get_bw_state(state); > if (IS_ERR(new_bw_state)) > return PTR_ERR(new_bw_state); > > - cdclk_state = intel_atomic_get_cdclk_state(state); > - if (IS_ERR(cdclk_state)) > - return PTR_ERR(cdclk_state); > - > - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > - > - new_bw_state->min_cdclk = min_cdclk; > - > old_bw_state = intel_atomic_get_old_bw_state(state); > } > > if (!old_bw_state) > return 0; > > + for_each_pipe(dev_priv, pipe) { > + struct intel_cdclk_state *cdclk_state; > + > + cdclk_state = intel_atomic_get_new_cdclk_state(state); > + if (!cdclk_state) > + return 0; > + > + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > + } > + > + new_bw_state->min_cdclk = min_cdclk; > + > if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > int ret = intel_atomic_lock_global_state(&new_bw_state->base); > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index f9b0fc7317de..08468b121d02 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2084,9 +2084,12 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > { > struct intel_atomic_state *state = cdclk_state->base.state; > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > + struct intel_bw_state *bw_state = NULL; > struct intel_crtc *crtc; > struct intel_crtc_state *crtc_state; > int min_cdclk, i; > + enum pipe pipe; > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > int ret; > @@ -2095,6 +2098,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > if (min_cdclk < 0) > return min_cdclk; > > + bw_state = intel_atomic_get_bw_state(state); > + if (IS_ERR(bw_state)) > + return PTR_ERR(bw_state); > + > if (cdclk_state->min_cdclk[i] == min_cdclk) > continue; > > @@ -2106,15 +2113,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > } > > min_cdclk = cdclk_state->force_min_cdclk; > + for_each_pipe(dev_priv, pipe) { > + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > > - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > - struct intel_bw_state *bw_state; > - > - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > - > - bw_state = intel_atomic_get_bw_state(state); > - if (IS_ERR(bw_state)) > - return PTR_ERR(bw_state); > + if (!bw_state) > + continue; > > min_cdclk = max(bw_state->min_cdclk, min_cdclk); > } > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index f40b909952cc..66af8f3053ed 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -14708,13 +14708,14 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, > bool *need_cdclk_calc) > { > struct drm_i915_private *dev_priv = to_i915(state->base.dev); > - int i; > + struct intel_cdclk_state *new_cdclk_state; > struct intel_plane_state *plane_state; > + struct intel_bw_state *new_bw_state; > struct intel_plane *plane; > + int min_cdclk = 0; > + enum pipe pipe; > int ret; > - struct intel_cdclk_state *new_cdclk_state; > - struct intel_crtc_state *new_crtc_state; > - struct intel_crtc *crtc; > + int i; > /* > * active_planes bitmask has been updated, and potentially > * affected planes are part of the state. We can now > @@ -14735,23 +14736,18 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, > if (ret) > return ret; > > - if (!new_cdclk_state) > - return 0; > - > - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > - struct intel_bw_state *bw_state; > - int min_cdclk = 0; > + new_bw_state = intel_atomic_get_new_bw_state(state); > > - min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > + if (!new_cdclk_state || !new_bw_state) > + return 0; > > - bw_state = intel_atomic_get_bw_state(state); > - if (IS_ERR(bw_state)) > - return PTR_ERR(bw_state); > + for_each_pipe(dev_priv, pipe) { > + min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); > > /* > * Currently do this change only if we need to increase > */ > - if (bw_state->min_cdclk > min_cdclk) > + if (new_bw_state->min_cdclk > min_cdclk) > *need_cdclk_calc = true; > } > > -- > 2.24.1.485.gad05a3d8e5 >
Hi Stanislav, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-tip/drm-tip] [also build test WARNING on drm-intel/drm-intel-next-queued] [cannot apply to drm-intel/for-linux-next v5.7-rc7 next-20200529] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Stanislav-Lisovskiy/drm-i915-Fix-wrong-CDCLK-adjustment-changes/20200526-180642 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kbuild test robot <lkp@intel.com> cppcheck warnings: (new ones prefixed by >>) >> drivers/gpu/drm/i915/display/intel_bw.c:453:36: warning: Uninitialized variable: pipe [uninitvar] crtc_bw = &new_bw_state->dbuf_bw[pipe]; ^ vim +453 drivers/gpu/drm/i915/display/intel_bw.c 430 431 int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) 432 { 433 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 434 struct intel_bw_state *new_bw_state = NULL; 435 struct intel_bw_state *old_bw_state = NULL; 436 const struct intel_crtc_state *crtc_state; 437 struct intel_crtc *crtc; 438 int max_bw = 0; 439 int slice_id; 440 enum pipe pipe; 441 int i; 442 443 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 444 enum plane_id plane_id; 445 struct intel_dbuf_bw *crtc_bw; 446 447 new_bw_state = intel_atomic_get_bw_state(state); 448 if (IS_ERR(new_bw_state)) 449 return PTR_ERR(new_bw_state); 450 451 old_bw_state = intel_atomic_get_old_bw_state(state); 452 > 453 crtc_bw = &new_bw_state->dbuf_bw[pipe]; 454 455 memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); 456 457 for_each_plane_id_on_crtc(crtc, plane_id) { 458 const struct skl_ddb_entry *plane_alloc = 459 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 460 const struct skl_ddb_entry *uv_plane_alloc = 461 &crtc_state->wm.skl.plane_ddb_uv[plane_id]; 462 unsigned int data_rate = crtc_state->data_rate[plane_id]; 463 unsigned int dbuf_mask = 0; 464 465 dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, plane_alloc); 466 dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc); 467 468 /* 469 * FIXME: To calculate that more properly we probably 470 * need to to split per plane data_rate into data_rate_y 471 * and data_rate_uv for multiplanar formats in order not 472 * to get accounted those twice if they happen to reside 473 * on different slices. 474 * However for pre-icl this would work anyway because 475 * we have only single slice and for icl+ uv plane has 476 * non-zero data rate. 477 * So in worst case those calculation are a bit 478 * pessimistic, which shouldn't pose any significant 479 * problem anyway. 480 */ 481 for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) 482 crtc_bw->used_bw[slice_id] += data_rate; 483 } 484 } 485 486 if (!old_bw_state) 487 return 0; 488 489 for_each_pipe(dev_priv, pipe) { 490 struct intel_dbuf_bw *crtc_bw; 491 492 crtc_bw = &new_bw_state->dbuf_bw[pipe]; 493 494 for_each_dbuf_slice(slice_id) { 495 /* 496 * Current experimental observations show that contrary 497 * to BSpec we get underruns once we exceed 64 * CDCLK 498 * for slices in total. 499 * As a temporary measure in order not to keep CDCLK 500 * bumped up all the time we calculate CDCLK according 501 * to this formula for overall bw consumed by slices. 502 */ 503 max_bw += crtc_bw->used_bw[slice_id]; 504 } 505 } 506 507 new_bw_state->min_cdclk = max_bw / 64; 508 509 if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { 510 int ret = intel_atomic_lock_global_state(&new_bw_state->base); 511 512 if (ret) 513 return ret; 514 } 515 516 return 0; 517 } 518 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
On Fri, May 29, 2020 at 04:57:38PM -0700, Manasi Navare wrote: > On Tue, May 26, 2020 at 12:48:52PM +0300, Stanislav Lisovskiy wrote: > > Previous patch didn't take into account all pipes > > but only those in state, which could cause wrong > > CDCLK conclcusions and calculations. > > Also there was a severe issue with min_cdclk being > > assigned to 0 every compare cycle. > > > > Too bad this was found by me only after merge. > > This could be also causing the issues in test, however > > not clear - anyway marking this as fixing the > > "Adjust CDCLK accordingly to our DBuf bw needs". > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > Fixes: cd1915460861 ("Adjust CDCLK accordingly to our DBuf bw needs") > > --- > > drivers/gpu/drm/i915/display/intel_bw.c | 51 ++++++++++++-------- > > drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +++++--- > > drivers/gpu/drm/i915/display/intel_display.c | 26 +++++----- > > 3 files changed, 53 insertions(+), 43 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > > index a79bd7aeb03b..8096138abecc 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bw.c > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > > @@ -437,6 +437,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > struct intel_crtc *crtc; > > int max_bw = 0; > > int slice_id; > > + enum pipe pipe; > > int i; > > > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > @@ -447,7 +448,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > if (IS_ERR(new_bw_state)) > > return PTR_ERR(new_bw_state); > > > > - crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe]; > > + old_bw_state = intel_atomic_get_old_bw_state(state); > > + > > + crtc_bw = &new_bw_state->dbuf_bw[pipe]; > > > > memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); > > > > @@ -478,6 +481,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) > > crtc_bw->used_bw[slice_id] += data_rate; > > } > > + } > > + > > + if (!old_bw_state) > > + return 0; > > + > > + for_each_pipe(dev_priv, pipe) { > > + struct intel_dbuf_bw *crtc_bw; > > + > > So the condition !old_bw_state() will make sure we loop through > only the active pipes and compute crtc_bw only for those right? > > Manasi Well, in fact this condition just checks if we had any crtcs in state - otherwise there were no changes, so bw_state global object doesn't need to be changed. Whenever something happens to crtc we should have it in the state, so this condition just checks if we need to modify bw_state or not. Regarding active/inactive pipes - currently for inactive pipes, we are going to get 0 dbuf slice mask, so we just won't accumulate any data rate for those. So if the pipe got disabled we will get less required min_cdclk which against old_bw_state, which will mean that we are going to acquire the global state lock for writing. In fact we could optimize the code by skipping inactive pipes completely i.e don't even calculate dbuf slice mask, which will be 0. However the logic and the end result would be the same anyway. Stan > > > + crtc_bw = &new_bw_state->dbuf_bw[pipe]; > > > > for_each_dbuf_slice(slice_id) { > > /* > > @@ -490,14 +502,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > */ > > max_bw += crtc_bw->used_bw[slice_id]; > > } > > - > > - new_bw_state->min_cdclk = max_bw / 64; > > - > > - old_bw_state = intel_atomic_get_old_bw_state(state); > > } > > > > - if (!old_bw_state) > > - return 0; > > + new_bw_state->min_cdclk = max_bw / 64; > > > > if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > > int ret = intel_atomic_lock_global_state(&new_bw_state->base); > > @@ -511,34 +518,38 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > > > int intel_bw_calc_min_cdclk(struct intel_atomic_state *state) > > { > > - int i; > > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > > + struct intel_bw_state *new_bw_state = NULL; > > + struct intel_bw_state *old_bw_state = NULL; > > const struct intel_crtc_state *crtc_state; > > struct intel_crtc *crtc; > > int min_cdclk = 0; > > - struct intel_bw_state *new_bw_state = NULL; > > - struct intel_bw_state *old_bw_state = NULL; > > + enum pipe pipe; > > + int i; > > > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > - struct intel_cdclk_state *cdclk_state; > > - > > new_bw_state = intel_atomic_get_bw_state(state); > > if (IS_ERR(new_bw_state)) > > return PTR_ERR(new_bw_state); > > > > - cdclk_state = intel_atomic_get_cdclk_state(state); > > - if (IS_ERR(cdclk_state)) > > - return PTR_ERR(cdclk_state); > > - > > - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > > - > > - new_bw_state->min_cdclk = min_cdclk; > > - > > old_bw_state = intel_atomic_get_old_bw_state(state); > > } > > > > if (!old_bw_state) > > return 0; > > > > + for_each_pipe(dev_priv, pipe) { > > + struct intel_cdclk_state *cdclk_state; > > + > > + cdclk_state = intel_atomic_get_new_cdclk_state(state); > > + if (!cdclk_state) > > + return 0; > > + > > + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > > + } > > + > > + new_bw_state->min_cdclk = min_cdclk; > > + > > if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > > int ret = intel_atomic_lock_global_state(&new_bw_state->base); > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > > index f9b0fc7317de..08468b121d02 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > @@ -2084,9 +2084,12 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > > static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > > { > > struct intel_atomic_state *state = cdclk_state->base.state; > > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > > + struct intel_bw_state *bw_state = NULL; > > struct intel_crtc *crtc; > > struct intel_crtc_state *crtc_state; > > int min_cdclk, i; > > + enum pipe pipe; > > > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > int ret; > > @@ -2095,6 +2098,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > > if (min_cdclk < 0) > > return min_cdclk; > > > > + bw_state = intel_atomic_get_bw_state(state); > > + if (IS_ERR(bw_state)) > > + return PTR_ERR(bw_state); > > + > > if (cdclk_state->min_cdclk[i] == min_cdclk) > > continue; > > > > @@ -2106,15 +2113,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > > } > > > > min_cdclk = cdclk_state->force_min_cdclk; > > + for_each_pipe(dev_priv, pipe) { > > + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > > > > - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > - struct intel_bw_state *bw_state; > > - > > - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > > - > > - bw_state = intel_atomic_get_bw_state(state); > > - if (IS_ERR(bw_state)) > > - return PTR_ERR(bw_state); > > + if (!bw_state) > > + continue; > > > > min_cdclk = max(bw_state->min_cdclk, min_cdclk); > > } > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index f40b909952cc..66af8f3053ed 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -14708,13 +14708,14 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, > > bool *need_cdclk_calc) > > { > > struct drm_i915_private *dev_priv = to_i915(state->base.dev); > > - int i; > > + struct intel_cdclk_state *new_cdclk_state; > > struct intel_plane_state *plane_state; > > + struct intel_bw_state *new_bw_state; > > struct intel_plane *plane; > > + int min_cdclk = 0; > > + enum pipe pipe; > > int ret; > > - struct intel_cdclk_state *new_cdclk_state; > > - struct intel_crtc_state *new_crtc_state; > > - struct intel_crtc *crtc; > > + int i; > > /* > > * active_planes bitmask has been updated, and potentially > > * affected planes are part of the state. We can now > > @@ -14735,23 +14736,18 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, > > if (ret) > > return ret; > > > > - if (!new_cdclk_state) > > - return 0; > > - > > - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > > - struct intel_bw_state *bw_state; > > - int min_cdclk = 0; > > + new_bw_state = intel_atomic_get_new_bw_state(state); > > > > - min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > > + if (!new_cdclk_state || !new_bw_state) > > + return 0; > > > > - bw_state = intel_atomic_get_bw_state(state); > > - if (IS_ERR(bw_state)) > > - return PTR_ERR(bw_state); > > + for_each_pipe(dev_priv, pipe) { > > + min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); > > > > /* > > * Currently do this change only if we need to increase > > */ > > - if (bw_state->min_cdclk > min_cdclk) > > + if (new_bw_state->min_cdclk > min_cdclk) > > *need_cdclk_calc = true; > > } > > > > -- > > 2.24.1.485.gad05a3d8e5 > >
Hi Stanislav,
url: https://github.com/0day-ci/linux/commits/Stanislav-Lisovskiy/drm-i915-Fix-wrong-CDCLK-adjustment-changes/20200526-180642
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-m021-20200531 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-13) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
smatch warnings:
drivers/gpu/drm/i915/display/intel_bw.c:453 skl_bw_calc_min_cdclk() error: uninitialized symbol 'pipe'.
# https://github.com/0day-ci/linux/commit/21b0324886122a396687d977d67eb6ce3caf2b17
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout 21b0324886122a396687d977d67eb6ce3caf2b17
vim +/pipe +453 drivers/gpu/drm/i915/display/intel_bw.c
366b6200f76e0f Jani Nikula 2019-08-06 430
cd19154608610a Stanislav Lisovskiy 2020-05-20 431 int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)
cd19154608610a Stanislav Lisovskiy 2020-05-20 432 {
cd19154608610a Stanislav Lisovskiy 2020-05-20 433 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 434 struct intel_bw_state *new_bw_state = NULL;
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 435 struct intel_bw_state *old_bw_state = NULL;
cd19154608610a Stanislav Lisovskiy 2020-05-20 436 const struct intel_crtc_state *crtc_state;
cd19154608610a Stanislav Lisovskiy 2020-05-20 437 struct intel_crtc *crtc;
cd19154608610a Stanislav Lisovskiy 2020-05-20 438 int max_bw = 0;
cd19154608610a Stanislav Lisovskiy 2020-05-20 439 int slice_id;
21b0324886122a Stanislav Lisovskiy 2020-05-26 440 enum pipe pipe;
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 441 int i;
cd19154608610a Stanislav Lisovskiy 2020-05-20 442
cd19154608610a Stanislav Lisovskiy 2020-05-20 443 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
cd19154608610a Stanislav Lisovskiy 2020-05-20 444 enum plane_id plane_id;
cd19154608610a Stanislav Lisovskiy 2020-05-20 445 struct intel_dbuf_bw *crtc_bw;
cd19154608610a Stanislav Lisovskiy 2020-05-20 446
cd19154608610a Stanislav Lisovskiy 2020-05-20 447 new_bw_state = intel_atomic_get_bw_state(state);
cd19154608610a Stanislav Lisovskiy 2020-05-20 448 if (IS_ERR(new_bw_state))
cd19154608610a Stanislav Lisovskiy 2020-05-20 449 return PTR_ERR(new_bw_state);
cd19154608610a Stanislav Lisovskiy 2020-05-20 450
21b0324886122a Stanislav Lisovskiy 2020-05-26 451 old_bw_state = intel_atomic_get_old_bw_state(state);
21b0324886122a Stanislav Lisovskiy 2020-05-26 452
21b0324886122a Stanislav Lisovskiy 2020-05-26 @453 crtc_bw = &new_bw_state->dbuf_bw[pipe];
^^^^
Not initialized. Probably "i" was intended?
cd19154608610a Stanislav Lisovskiy 2020-05-20 454
cd19154608610a Stanislav Lisovskiy 2020-05-20 455 memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));
cd19154608610a Stanislav Lisovskiy 2020-05-20 456
cd19154608610a Stanislav Lisovskiy 2020-05-20 457 for_each_plane_id_on_crtc(crtc, plane_id) {
cd19154608610a Stanislav Lisovskiy 2020-05-20 458 const struct skl_ddb_entry *plane_alloc =
cd19154608610a Stanislav Lisovskiy 2020-05-20 459 &crtc_state->wm.skl.plane_ddb_y[plane_id];
cd19154608610a Stanislav Lisovskiy 2020-05-20 460 const struct skl_ddb_entry *uv_plane_alloc =
cd19154608610a Stanislav Lisovskiy 2020-05-20 461 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
cd19154608610a Stanislav Lisovskiy 2020-05-20 462 unsigned int data_rate = crtc_state->data_rate[plane_id];
cd19154608610a Stanislav Lisovskiy 2020-05-20 463 unsigned int dbuf_mask = 0;
cd19154608610a Stanislav Lisovskiy 2020-05-20 464
cd19154608610a Stanislav Lisovskiy 2020-05-20 465 dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, plane_alloc);
cd19154608610a Stanislav Lisovskiy 2020-05-20 466 dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc);
cd19154608610a Stanislav Lisovskiy 2020-05-20 467
cd19154608610a Stanislav Lisovskiy 2020-05-20 468 /*
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 469 * FIXME: To calculate that more properly we probably
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 470 * need to to split per plane data_rate into data_rate_y
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 471 * and data_rate_uv for multiplanar formats in order not
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 472 * to get accounted those twice if they happen to reside
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 473 * on different slices.
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 474 * However for pre-icl this would work anyway because
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 475 * we have only single slice and for icl+ uv plane has
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 476 * non-zero data rate.
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 477 * So in worst case those calculation are a bit
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 478 * pessimistic, which shouldn't pose any significant
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 479 * problem anyway.
cd19154608610a Stanislav Lisovskiy 2020-05-20 480 */
cd19154608610a Stanislav Lisovskiy 2020-05-20 481 for_each_dbuf_slice_in_mask(slice_id, dbuf_mask)
cd19154608610a Stanislav Lisovskiy 2020-05-20 482 crtc_bw->used_bw[slice_id] += data_rate;
cd19154608610a Stanislav Lisovskiy 2020-05-20 483 }
21b0324886122a Stanislav Lisovskiy 2020-05-26 484 }
21b0324886122a Stanislav Lisovskiy 2020-05-26 485
21b0324886122a Stanislav Lisovskiy 2020-05-26 486 if (!old_bw_state)
21b0324886122a Stanislav Lisovskiy 2020-05-26 487 return 0;
21b0324886122a Stanislav Lisovskiy 2020-05-26 488
21b0324886122a Stanislav Lisovskiy 2020-05-26 489 for_each_pipe(dev_priv, pipe) {
21b0324886122a Stanislav Lisovskiy 2020-05-26 490 struct intel_dbuf_bw *crtc_bw;
21b0324886122a Stanislav Lisovskiy 2020-05-26 491
21b0324886122a Stanislav Lisovskiy 2020-05-26 492 crtc_bw = &new_bw_state->dbuf_bw[pipe];
cd19154608610a Stanislav Lisovskiy 2020-05-20 493
cd19154608610a Stanislav Lisovskiy 2020-05-20 494 for_each_dbuf_slice(slice_id) {
cd19154608610a Stanislav Lisovskiy 2020-05-20 495 /*
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 496 * Current experimental observations show that contrary
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 497 * to BSpec we get underruns once we exceed 64 * CDCLK
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 498 * for slices in total.
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 499 * As a temporary measure in order not to keep CDCLK
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 500 * bumped up all the time we calculate CDCLK according
cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 501 * to this formula for overall bw consumed by slices.
cd19154608610a Stanislav Lisovskiy 2020-05-20 502 */
cd19154608610a Stanislav Lisovskiy 2020-05-20 503 max_bw += crtc_bw->used_bw[slice_id];
cd19154608610a Stanislav Lisovskiy 2020-05-20 504 }
cd19154608610a Stanislav Lisovskiy 2020-05-20 505 }
cd19154608610a Stanislav Lisovskiy 2020-05-20 506
21b0324886122a Stanislav Lisovskiy 2020-05-26 507 new_bw_state->min_cdclk = max_bw / 64;
cd19154608610a Stanislav Lisovskiy 2020-05-20 508
cd19154608610a Stanislav Lisovskiy 2020-05-20 509 if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) {
cd19154608610a Stanislav Lisovskiy 2020-05-20 510 int ret = intel_atomic_lock_global_state(&new_bw_state->base);
cd19154608610a Stanislav Lisovskiy 2020-05-20 511
cd19154608610a Stanislav Lisovskiy 2020-05-20 512 if (ret)
cd19154608610a Stanislav Lisovskiy 2020-05-20 513 return ret;
cd19154608610a Stanislav Lisovskiy 2020-05-20 514 }
cd19154608610a Stanislav Lisovskiy 2020-05-20 515
cd19154608610a Stanislav Lisovskiy 2020-05-20 516 return 0;
cd19154608610a Stanislav Lisovskiy 2020-05-20 517 }
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
On Mon, Jun 01, 2020 at 05:01:08PM +0300, Dan Carpenter wrote: > Hi Stanislav, > > url: https://github.com/0day-ci/linux/commits/Stanislav-Lisovskiy/drm-i915-Fix-wrong-CDCLK-adjustment-changes/20200526-180642 > base: git://anongit.freedesktop.org/drm/drm-tip drm-tip > config: i386-randconfig-m021-20200531 (attached as .config) > compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 > > If you fix the issue, kindly add following tag as appropriate > Reported-by: kbuild test robot <lkp@intel.com> > Reported-by: Dan Carpenter <dan.carpenter@oracle.com> > > smatch warnings: > drivers/gpu/drm/i915/display/intel_bw.c:453 skl_bw_calc_min_cdclk() error: uninitialized symbol 'pipe'. > > # https://github.com/0day-ci/linux/commit/21b0324886122a396687d977d67eb6ce3caf2b17 > git remote add linux-review https://github.com/0day-ci/linux > git remote update linux-review > git checkout 21b0324886122a396687d977d67eb6ce3caf2b17 > vim +/pipe +453 drivers/gpu/drm/i915/display/intel_bw.c > > 366b6200f76e0f Jani Nikula 2019-08-06 430 > cd19154608610a Stanislav Lisovskiy 2020-05-20 431 int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > cd19154608610a Stanislav Lisovskiy 2020-05-20 432 { > cd19154608610a Stanislav Lisovskiy 2020-05-20 433 struct drm_i915_private *dev_priv = to_i915(state->base.dev); > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 434 struct intel_bw_state *new_bw_state = NULL; > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 435 struct intel_bw_state *old_bw_state = NULL; > cd19154608610a Stanislav Lisovskiy 2020-05-20 436 const struct intel_crtc_state *crtc_state; > cd19154608610a Stanislav Lisovskiy 2020-05-20 437 struct intel_crtc *crtc; > cd19154608610a Stanislav Lisovskiy 2020-05-20 438 int max_bw = 0; > cd19154608610a Stanislav Lisovskiy 2020-05-20 439 int slice_id; > 21b0324886122a Stanislav Lisovskiy 2020-05-26 440 enum pipe pipe; > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 441 int i; > cd19154608610a Stanislav Lisovskiy 2020-05-20 442 > cd19154608610a Stanislav Lisovskiy 2020-05-20 443 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > cd19154608610a Stanislav Lisovskiy 2020-05-20 444 enum plane_id plane_id; > cd19154608610a Stanislav Lisovskiy 2020-05-20 445 struct intel_dbuf_bw *crtc_bw; > cd19154608610a Stanislav Lisovskiy 2020-05-20 446 > cd19154608610a Stanislav Lisovskiy 2020-05-20 447 new_bw_state = intel_atomic_get_bw_state(state); > cd19154608610a Stanislav Lisovskiy 2020-05-20 448 if (IS_ERR(new_bw_state)) > cd19154608610a Stanislav Lisovskiy 2020-05-20 449 return PTR_ERR(new_bw_state); > cd19154608610a Stanislav Lisovskiy 2020-05-20 450 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 451 old_bw_state = intel_atomic_get_old_bw_state(state); > 21b0324886122a Stanislav Lisovskiy 2020-05-26 452 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 @453 crtc_bw = &new_bw_state->dbuf_bw[pipe]; > ^^^^ > Not initialized. Probably "i" was intended? Ahh.. Rather silly typo - it should be crtc->pipe. Thanks for spotting. Stan > > cd19154608610a Stanislav Lisovskiy 2020-05-20 454 > cd19154608610a Stanislav Lisovskiy 2020-05-20 455 memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); > cd19154608610a Stanislav Lisovskiy 2020-05-20 456 > cd19154608610a Stanislav Lisovskiy 2020-05-20 457 for_each_plane_id_on_crtc(crtc, plane_id) { > cd19154608610a Stanislav Lisovskiy 2020-05-20 458 const struct skl_ddb_entry *plane_alloc = > cd19154608610a Stanislav Lisovskiy 2020-05-20 459 &crtc_state->wm.skl.plane_ddb_y[plane_id]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 460 const struct skl_ddb_entry *uv_plane_alloc = > cd19154608610a Stanislav Lisovskiy 2020-05-20 461 &crtc_state->wm.skl.plane_ddb_uv[plane_id]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 462 unsigned int data_rate = crtc_state->data_rate[plane_id]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 463 unsigned int dbuf_mask = 0; > cd19154608610a Stanislav Lisovskiy 2020-05-20 464 > cd19154608610a Stanislav Lisovskiy 2020-05-20 465 dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, plane_alloc); > cd19154608610a Stanislav Lisovskiy 2020-05-20 466 dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc); > cd19154608610a Stanislav Lisovskiy 2020-05-20 467 > cd19154608610a Stanislav Lisovskiy 2020-05-20 468 /* > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 469 * FIXME: To calculate that more properly we probably > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 470 * need to to split per plane data_rate into data_rate_y > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 471 * and data_rate_uv for multiplanar formats in order not > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 472 * to get accounted those twice if they happen to reside > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 473 * on different slices. > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 474 * However for pre-icl this would work anyway because > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 475 * we have only single slice and for icl+ uv plane has > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 476 * non-zero data rate. > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 477 * So in worst case those calculation are a bit > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 478 * pessimistic, which shouldn't pose any significant > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 479 * problem anyway. > cd19154608610a Stanislav Lisovskiy 2020-05-20 480 */ > cd19154608610a Stanislav Lisovskiy 2020-05-20 481 for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) > cd19154608610a Stanislav Lisovskiy 2020-05-20 482 crtc_bw->used_bw[slice_id] += data_rate; > cd19154608610a Stanislav Lisovskiy 2020-05-20 483 } > 21b0324886122a Stanislav Lisovskiy 2020-05-26 484 } > 21b0324886122a Stanislav Lisovskiy 2020-05-26 485 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 486 if (!old_bw_state) > 21b0324886122a Stanislav Lisovskiy 2020-05-26 487 return 0; > 21b0324886122a Stanislav Lisovskiy 2020-05-26 488 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 489 for_each_pipe(dev_priv, pipe) { > 21b0324886122a Stanislav Lisovskiy 2020-05-26 490 struct intel_dbuf_bw *crtc_bw; > 21b0324886122a Stanislav Lisovskiy 2020-05-26 491 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 492 crtc_bw = &new_bw_state->dbuf_bw[pipe]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 493 > cd19154608610a Stanislav Lisovskiy 2020-05-20 494 for_each_dbuf_slice(slice_id) { > cd19154608610a Stanislav Lisovskiy 2020-05-20 495 /* > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 496 * Current experimental observations show that contrary > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 497 * to BSpec we get underruns once we exceed 64 * CDCLK > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 498 * for slices in total. > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 499 * As a temporary measure in order not to keep CDCLK > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 500 * bumped up all the time we calculate CDCLK according > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 501 * to this formula for overall bw consumed by slices. > cd19154608610a Stanislav Lisovskiy 2020-05-20 502 */ > cd19154608610a Stanislav Lisovskiy 2020-05-20 503 max_bw += crtc_bw->used_bw[slice_id]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 504 } > cd19154608610a Stanislav Lisovskiy 2020-05-20 505 } > cd19154608610a Stanislav Lisovskiy 2020-05-20 506 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 507 new_bw_state->min_cdclk = max_bw / 64; > cd19154608610a Stanislav Lisovskiy 2020-05-20 508 > cd19154608610a Stanislav Lisovskiy 2020-05-20 509 if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > cd19154608610a Stanislav Lisovskiy 2020-05-20 510 int ret = intel_atomic_lock_global_state(&new_bw_state->base); > cd19154608610a Stanislav Lisovskiy 2020-05-20 511 > cd19154608610a Stanislav Lisovskiy 2020-05-20 512 if (ret) > cd19154608610a Stanislav Lisovskiy 2020-05-20 513 return ret; > cd19154608610a Stanislav Lisovskiy 2020-05-20 514 } > cd19154608610a Stanislav Lisovskiy 2020-05-20 515 > cd19154608610a Stanislav Lisovskiy 2020-05-20 516 return 0; > cd19154608610a Stanislav Lisovskiy 2020-05-20 517 } > > --- > 0-DAY CI Kernel Test Service, Intel Corporation > https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
On Mon, Jun 01, 2020 at 10:49:54AM +0300, Lisovskiy, Stanislav wrote: > On Fri, May 29, 2020 at 04:57:38PM -0700, Manasi Navare wrote: > > On Tue, May 26, 2020 at 12:48:52PM +0300, Stanislav Lisovskiy wrote: > > > Previous patch didn't take into account all pipes > > > but only those in state, which could cause wrong > > > CDCLK conclcusions and calculations. > > > Also there was a severe issue with min_cdclk being > > > assigned to 0 every compare cycle. > > > > > > Too bad this was found by me only after merge. > > > This could be also causing the issues in test, however > > > not clear - anyway marking this as fixing the > > > "Adjust CDCLK accordingly to our DBuf bw needs". > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > > Fixes: cd1915460861 ("Adjust CDCLK accordingly to our DBuf bw needs") > > > --- > > > drivers/gpu/drm/i915/display/intel_bw.c | 51 ++++++++++++-------- > > > drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +++++--- > > > drivers/gpu/drm/i915/display/intel_display.c | 26 +++++----- > > > 3 files changed, 53 insertions(+), 43 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > > > index a79bd7aeb03b..8096138abecc 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_bw.c > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > > > @@ -437,6 +437,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > > struct intel_crtc *crtc; > > > int max_bw = 0; > > > int slice_id; > > > + enum pipe pipe; > > > int i; > > > > > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > > @@ -447,7 +448,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > > if (IS_ERR(new_bw_state)) > > > return PTR_ERR(new_bw_state); > > > > > > - crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe]; > > > + old_bw_state = intel_atomic_get_old_bw_state(state); > > > + > > > + crtc_bw = &new_bw_state->dbuf_bw[pipe]; > > > > > > memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); > > > > > > @@ -478,6 +481,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > > for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) > > > crtc_bw->used_bw[slice_id] += data_rate; > > > } > > > + } > > > + > > > + if (!old_bw_state) > > > + return 0; > > > + > > > + for_each_pipe(dev_priv, pipe) { > > > + struct intel_dbuf_bw *crtc_bw; > > > + > > > > So the condition !old_bw_state() will make sure we loop through > > only the active pipes and compute crtc_bw only for those right? > > > > Manasi > > Well, in fact this condition just checks if we had any crtcs in state - > otherwise there were no changes, so bw_state global object doesn't need > to be changed. Whenever something happens to crtc we should have it > in the state, so this condition just checks if we need to modify bw_state > or not. > > Regarding active/inactive pipes - currently for inactive pipes, > we are going to get 0 dbuf slice mask, so we just won't accumulate any data > rate for those. So if the pipe got disabled we will get less required min_cdclk > which against old_bw_state, which will mean that we are going to acquire > the global state lock for writing. > > In fact we could optimize the code by skipping inactive pipes completely > i.e don't even calculate dbuf slice mask, > which will be 0. However the logic and the end result would be > the same anyway. Okay yes this makes sense, thanks for the clarification. So would be it be an easy change to add a condition to return for an inactive pipe? Manasi > > Stan > > > > > > + crtc_bw = &new_bw_state->dbuf_bw[pipe]; > > > > > > for_each_dbuf_slice(slice_id) { > > > /* > > > @@ -490,14 +502,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > > */ > > > max_bw += crtc_bw->used_bw[slice_id]; > > > } > > > - > > > - new_bw_state->min_cdclk = max_bw / 64; > > > - > > > - old_bw_state = intel_atomic_get_old_bw_state(state); > > > } > > > > > > - if (!old_bw_state) > > > - return 0; > > > + new_bw_state->min_cdclk = max_bw / 64; > > > > > > if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > > > int ret = intel_atomic_lock_global_state(&new_bw_state->base); > > > @@ -511,34 +518,38 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > > > > > int intel_bw_calc_min_cdclk(struct intel_atomic_state *state) > > > { > > > - int i; > > > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > > > + struct intel_bw_state *new_bw_state = NULL; > > > + struct intel_bw_state *old_bw_state = NULL; > > > const struct intel_crtc_state *crtc_state; > > > struct intel_crtc *crtc; > > > int min_cdclk = 0; > > > - struct intel_bw_state *new_bw_state = NULL; > > > - struct intel_bw_state *old_bw_state = NULL; > > > + enum pipe pipe; > > > + int i; > > > > > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > > - struct intel_cdclk_state *cdclk_state; > > > - > > > new_bw_state = intel_atomic_get_bw_state(state); > > > if (IS_ERR(new_bw_state)) > > > return PTR_ERR(new_bw_state); > > > > > > - cdclk_state = intel_atomic_get_cdclk_state(state); > > > - if (IS_ERR(cdclk_state)) > > > - return PTR_ERR(cdclk_state); > > > - > > > - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > > > - > > > - new_bw_state->min_cdclk = min_cdclk; > > > - > > > old_bw_state = intel_atomic_get_old_bw_state(state); > > > } > > > > > > if (!old_bw_state) > > > return 0; > > > > > > + for_each_pipe(dev_priv, pipe) { > > > + struct intel_cdclk_state *cdclk_state; > > > + > > > + cdclk_state = intel_atomic_get_new_cdclk_state(state); > > > + if (!cdclk_state) > > > + return 0; > > > + > > > + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > > > + } > > > + > > > + new_bw_state->min_cdclk = min_cdclk; > > > + > > > if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > > > int ret = intel_atomic_lock_global_state(&new_bw_state->base); > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > > > index f9b0fc7317de..08468b121d02 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > > @@ -2084,9 +2084,12 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > > > static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > > > { > > > struct intel_atomic_state *state = cdclk_state->base.state; > > > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > > > + struct intel_bw_state *bw_state = NULL; > > > struct intel_crtc *crtc; > > > struct intel_crtc_state *crtc_state; > > > int min_cdclk, i; > > > + enum pipe pipe; > > > > > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > > int ret; > > > @@ -2095,6 +2098,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > > > if (min_cdclk < 0) > > > return min_cdclk; > > > > > > + bw_state = intel_atomic_get_bw_state(state); > > > + if (IS_ERR(bw_state)) > > > + return PTR_ERR(bw_state); > > > + > > > if (cdclk_state->min_cdclk[i] == min_cdclk) > > > continue; > > > > > > @@ -2106,15 +2113,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > > > } > > > > > > min_cdclk = cdclk_state->force_min_cdclk; > > > + for_each_pipe(dev_priv, pipe) { > > > + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > > > > > > - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > > - struct intel_bw_state *bw_state; > > > - > > > - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > > > - > > > - bw_state = intel_atomic_get_bw_state(state); > > > - if (IS_ERR(bw_state)) > > > - return PTR_ERR(bw_state); > > > + if (!bw_state) > > > + continue; > > > > > > min_cdclk = max(bw_state->min_cdclk, min_cdclk); > > > } > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > index f40b909952cc..66af8f3053ed 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -14708,13 +14708,14 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, > > > bool *need_cdclk_calc) > > > { > > > struct drm_i915_private *dev_priv = to_i915(state->base.dev); > > > - int i; > > > + struct intel_cdclk_state *new_cdclk_state; > > > struct intel_plane_state *plane_state; > > > + struct intel_bw_state *new_bw_state; > > > struct intel_plane *plane; > > > + int min_cdclk = 0; > > > + enum pipe pipe; > > > int ret; > > > - struct intel_cdclk_state *new_cdclk_state; > > > - struct intel_crtc_state *new_crtc_state; > > > - struct intel_crtc *crtc; > > > + int i; > > > /* > > > * active_planes bitmask has been updated, and potentially > > > * affected planes are part of the state. We can now > > > @@ -14735,23 +14736,18 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, > > > if (ret) > > > return ret; > > > > > > - if (!new_cdclk_state) > > > - return 0; > > > - > > > - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > > > - struct intel_bw_state *bw_state; > > > - int min_cdclk = 0; > > > + new_bw_state = intel_atomic_get_new_bw_state(state); > > > > > > - min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > > > + if (!new_cdclk_state || !new_bw_state) > > > + return 0; > > > > > > - bw_state = intel_atomic_get_bw_state(state); > > > - if (IS_ERR(bw_state)) > > > - return PTR_ERR(bw_state); > > > + for_each_pipe(dev_priv, pipe) { > > > + min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); > > > > > > /* > > > * Currently do this change only if we need to increase > > > */ > > > - if (bw_state->min_cdclk > min_cdclk) > > > + if (new_bw_state->min_cdclk > min_cdclk) > > > *need_cdclk_calc = true; > > > } > > > > > > -- > > > 2.24.1.485.gad05a3d8e5 > > >
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index a79bd7aeb03b..8096138abecc 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -437,6 +437,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) struct intel_crtc *crtc; int max_bw = 0; int slice_id; + enum pipe pipe; int i; for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { @@ -447,7 +448,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) if (IS_ERR(new_bw_state)) return PTR_ERR(new_bw_state); - crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe]; + old_bw_state = intel_atomic_get_old_bw_state(state); + + crtc_bw = &new_bw_state->dbuf_bw[pipe]; memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); @@ -478,6 +481,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) crtc_bw->used_bw[slice_id] += data_rate; } + } + + if (!old_bw_state) + return 0; + + for_each_pipe(dev_priv, pipe) { + struct intel_dbuf_bw *crtc_bw; + + crtc_bw = &new_bw_state->dbuf_bw[pipe]; for_each_dbuf_slice(slice_id) { /* @@ -490,14 +502,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) */ max_bw += crtc_bw->used_bw[slice_id]; } - - new_bw_state->min_cdclk = max_bw / 64; - - old_bw_state = intel_atomic_get_old_bw_state(state); } - if (!old_bw_state) - return 0; + new_bw_state->min_cdclk = max_bw / 64; if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { int ret = intel_atomic_lock_global_state(&new_bw_state->base); @@ -511,34 +518,38 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) int intel_bw_calc_min_cdclk(struct intel_atomic_state *state) { - int i; + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_bw_state *new_bw_state = NULL; + struct intel_bw_state *old_bw_state = NULL; const struct intel_crtc_state *crtc_state; struct intel_crtc *crtc; int min_cdclk = 0; - struct intel_bw_state *new_bw_state = NULL; - struct intel_bw_state *old_bw_state = NULL; + enum pipe pipe; + int i; for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { - struct intel_cdclk_state *cdclk_state; - new_bw_state = intel_atomic_get_bw_state(state); if (IS_ERR(new_bw_state)) return PTR_ERR(new_bw_state); - cdclk_state = intel_atomic_get_cdclk_state(state); - if (IS_ERR(cdclk_state)) - return PTR_ERR(cdclk_state); - - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); - - new_bw_state->min_cdclk = min_cdclk; - old_bw_state = intel_atomic_get_old_bw_state(state); } if (!old_bw_state) return 0; + for_each_pipe(dev_priv, pipe) { + struct intel_cdclk_state *cdclk_state; + + cdclk_state = intel_atomic_get_new_cdclk_state(state); + if (!cdclk_state) + return 0; + + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); + } + + new_bw_state->min_cdclk = min_cdclk; + if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { int ret = intel_atomic_lock_global_state(&new_bw_state->base); diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index f9b0fc7317de..08468b121d02 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2084,9 +2084,12 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) { struct intel_atomic_state *state = cdclk_state->base.state; + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_bw_state *bw_state = NULL; struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; int min_cdclk, i; + enum pipe pipe; for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { int ret; @@ -2095,6 +2098,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) if (min_cdclk < 0) return min_cdclk; + bw_state = intel_atomic_get_bw_state(state); + if (IS_ERR(bw_state)) + return PTR_ERR(bw_state); + if (cdclk_state->min_cdclk[i] == min_cdclk) continue; @@ -2106,15 +2113,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) } min_cdclk = cdclk_state->force_min_cdclk; + for_each_pipe(dev_priv, pipe) { + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { - struct intel_bw_state *bw_state; - - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); - - bw_state = intel_atomic_get_bw_state(state); - if (IS_ERR(bw_state)) - return PTR_ERR(bw_state); + if (!bw_state) + continue; min_cdclk = max(bw_state->min_cdclk, min_cdclk); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f40b909952cc..66af8f3053ed 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14708,13 +14708,14 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, bool *need_cdclk_calc) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - int i; + struct intel_cdclk_state *new_cdclk_state; struct intel_plane_state *plane_state; + struct intel_bw_state *new_bw_state; struct intel_plane *plane; + int min_cdclk = 0; + enum pipe pipe; int ret; - struct intel_cdclk_state *new_cdclk_state; - struct intel_crtc_state *new_crtc_state; - struct intel_crtc *crtc; + int i; /* * active_planes bitmask has been updated, and potentially * affected planes are part of the state. We can now @@ -14735,23 +14736,18 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, if (ret) return ret; - if (!new_cdclk_state) - return 0; - - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { - struct intel_bw_state *bw_state; - int min_cdclk = 0; + new_bw_state = intel_atomic_get_new_bw_state(state); - min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk); + if (!new_cdclk_state || !new_bw_state) + return 0; - bw_state = intel_atomic_get_bw_state(state); - if (IS_ERR(bw_state)) - return PTR_ERR(bw_state); + for_each_pipe(dev_priv, pipe) { + min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); /* * Currently do this change only if we need to increase */ - if (bw_state->min_cdclk > min_cdclk) + if (new_bw_state->min_cdclk > min_cdclk) *need_cdclk_calc = true; }
Previous patch didn't take into account all pipes but only those in state, which could cause wrong CDCLK conclcusions and calculations. Also there was a severe issue with min_cdclk being assigned to 0 every compare cycle. Too bad this was found by me only after merge. This could be also causing the issues in test, however not clear - anyway marking this as fixing the "Adjust CDCLK accordingly to our DBuf bw needs". Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: cd1915460861 ("Adjust CDCLK accordingly to our DBuf bw needs") --- drivers/gpu/drm/i915/display/intel_bw.c | 51 ++++++++++++-------- drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +++++--- drivers/gpu/drm/i915/display/intel_display.c | 26 +++++----- 3 files changed, 53 insertions(+), 43 deletions(-)