| Message ID | 20200607143614.185246-1-gwan-gyeong.mun@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v4] drm/i915/psr: Program default IO buffer Wake and Fast Wake | expand |
On Sun, 2020-06-07 at 17:36 +0300, Gwan-gyeong Mun wrote: > The IO buffer Wake and Fast Wake bit size and value have been changed from > Gen12+. It programs the default value of IO buffer Wake and Fast Wake on > Gen12+. It adds definitions of IO buffer Wake and Fast Wake for pre Gen12 > and Gen12+. And it aligns PSR2 definition macros. > > v2: Fix macro definitions. (José) > v3: Addressed review comments from José > - Add missing default values of IO_BUFFER_WAKE and FAST_WAKE for GEN9+ > - Change a style of macro naming in order to use lines as input. > - Update Todo comments. > v4: Add parentheses to macros to avoid precedence issues. > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > Cc: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 16 ++++++++ > drivers/gpu/drm/i915/i915_reg.h | 52 +++++++++++++++--------- > 2 files changed, 49 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 7a0011e42e00..ab380e6dc674 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -537,6 +537,22 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); > val |= intel_psr2_get_tp_time(intel_dp); > > + if (INTEL_GEN(dev_priv) >= 12) { > + /* > + * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default > + * values from BSpec. In order to setting an optimal power > + * consumption, lower than 4k resoluition mode needs to decrese > + * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution > + * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. > + */ > + val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; > + val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); > + val |= TGL_EDP_PSR2_FAST_WAKE(7); > + } else if (INTEL_GEN(dev_priv) >= 9) { > + val |= EDP_PSR2_IO_BUFFER_WAKE(7); > + val |= EDP_PSR2_FAST_WAKE(7); > + } > + > /* > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > * recommending keep this bit unset while PSR2 is enabled. > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 814a70945468..4066f67175dc 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4511,25 +4511,39 @@ enum { > #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ > #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ > > -#define _PSR2_CTL_A 0x60900 > -#define _PSR2_CTL_EDP 0x6f900 > -#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) > -#define EDP_PSR2_ENABLE (1 << 31) > -#define EDP_SU_TRACK_ENABLE (1 << 30) > -#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ > -#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ > -#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) > -#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) > -#define EDP_PSR2_TP2_TIME_500us (0 << 8) > -#define EDP_PSR2_TP2_TIME_100us (1 << 8) > -#define EDP_PSR2_TP2_TIME_2500us (2 << 8) > -#define EDP_PSR2_TP2_TIME_50us (3 << 8) > -#define EDP_PSR2_TP2_TIME_MASK (3 << 8) > -#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 > -#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) > -#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) > -#define EDP_PSR2_IDLE_FRAME_MASK 0xf > -#define EDP_PSR2_IDLE_FRAME_SHIFT 0 > +#define _PSR2_CTL_A 0x60900 > +#define _PSR2_CTL_EDP 0x6f900 > +#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) > +#define EDP_PSR2_ENABLE (1 << 31) > +#define EDP_SU_TRACK_ENABLE (1 << 30) > +#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) > +#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) > +#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ > +#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ > +#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) > +#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) > +#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 > +#define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) > +#define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13) > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) > +#define EDP_PSR2_FAST_WAKE_MAX_LINES 8 > +#define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11) > +#define EDP_PSR2_FAST_WAKE_MASK (3 << 11) > +#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 > +#define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10) > +#define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) > +#define EDP_PSR2_TP2_TIME_500us (0 << 8) > +#define EDP_PSR2_TP2_TIME_100us (1 << 8) > +#define EDP_PSR2_TP2_TIME_2500us (2 << 8) > +#define EDP_PSR2_TP2_TIME_50us (3 << 8) > +#define EDP_PSR2_TP2_TIME_MASK (3 << 8) > +#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 > +#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) > +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) > +#define EDP_PSR2_IDLE_FRAME_MASK 0xf > +#define EDP_PSR2_IDLE_FRAME_SHIFT 0 > > #define _PSR_EVENT_TRANS_A 0x60848 > #define _PSR_EVENT_TRANS_B 0x61848
On Sun, 2020-06-07 at 16:08 +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev4) > URL : https://patchwork.freedesktop.org/series/78019/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_8596_full -> Patchwork_17899_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. Pushed, thanks for the patch. > > > > Known issues > ------------ > > Here are the changes found in Patchwork_17899_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_partial_pwrite_pread@reads-snoop: > - shard-skl: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +7 similar issues > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl8/igt@gem_partial_pwrite_pread@reads-snoop.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl2/igt@gem_partial_pwrite_pread@reads-snoop.html > > * igt@i915_suspend@debugfs-reader: > - shard-kbl: [PASS][3] -> [INCOMPLETE][4] ([i915#155]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl6/igt@i915_suspend@debugfs-reader.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl2/igt@i915_suspend@debugfs-reader.html > > * igt@i915_suspend@forcewake: > - shard-apl: [PASS][5] -> [INCOMPLETE][6] ([i915#1630]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl7/igt@i915_suspend@forcewake.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl3/igt@i915_suspend@forcewake.html > > * igt@kms_big_fb@x-tiled-8bpp-rotate-0: > - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl4/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl6/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html > - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk6/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-glk1/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html > > * igt@kms_big_fb@y-tiled-64bpp-rotate-0: > - shard-glk: [PASS][11] -> [DMESG-FAIL][12] ([i915#118] / [i915#95]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk7/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-glk8/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html > > * igt@kms_color@pipe-c-ctm-blue-to-red: > - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#95]) +14 similar issues > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl3/igt@kms_color@pipe-c-ctm-blue-to-red.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl1/igt@kms_color@pipe-c-ctm-blue-to-red.html > > * igt@kms_cursor_crc@pipe-b-cursor-suspend: > - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#300]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-suspend.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html > > * igt@kms_cursor_legacy@pipe-c-torture-bo: > - shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([i915#128]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-hsw1/igt@kms_cursor_legacy@pipe-c-torture-bo.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-hsw5/igt@kms_cursor_legacy@pipe-c-torture-bo.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: > - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#93] / [i915#95]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html > > * igt@kms_hdr@bpc-switch-suspend: > - shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188]) > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html > > * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: > - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +1 similar issue > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html > > * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: > - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html > > * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: > - shard-skl: [PASS][27] -> [DMESG-FAIL][28] ([fdo#108145] / [i915#1982]) > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html > > * igt@kms_psr2_su@frontbuffer: > - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109642] / [fdo#111068]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb2/igt@kms_psr2_su@frontbuffer.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-iclb6/igt@kms_psr2_su@frontbuffer.html > > * igt@kms_psr@psr2_cursor_render: > - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +1 similar issue > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb2/igt@kms_psr@psr2_cursor_render.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-iclb8/igt@kms_psr@psr2_cursor_render.html > > * igt@kms_vblank@pipe-c-ts-continuation-suspend: > - shard-apl: [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +1 similar issue > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl3/igt@kms_vblank@pipe-c-ts-continuation-suspend.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html > > > #### Possible fixes #### > > * {igt@gem_exec_schedule@implicit-write-read@rcs0}: > - shard-snb: [INCOMPLETE][35] ([i915#82]) -> [PASS][36] +1 similar issue > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-snb4/igt@gem_exec_schedule@implicit-write-read@rcs0.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-snb1/igt@gem_exec_schedule@implicit-write-read@rcs0.html > > * igt@gem_exec_whisper@basic-normal: > - shard-glk: [DMESG-WARN][37] ([i915#118] / [i915#95]) -> [PASS][38] +1 similar issue > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk7/igt@gem_exec_whisper@basic-normal.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-glk8/igt@gem_exec_whisper@basic-normal.html > > * igt@gem_workarounds@suspend-resume-fd: > - shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +5 similar issues > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html > > * igt@kms_big_fb@x-tiled-16bpp-rotate-0: > - shard-glk: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk5/igt@kms_big_fb@x-tiled-16bpp-rotate-0.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-glk9/igt@kms_big_fb@x-tiled-16bpp-rotate-0.html > > * igt@kms_big_fb@yf-tiled-32bpp-rotate-0: > - shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +6 similar issues > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl10/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl5/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html > > * igt@kms_color@pipe-c-ctm-red-to-blue: > - shard-kbl: [DMESG-WARN][45] ([i915#93] / [i915#95]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt@kms_color@pipe-c-ctm-red-to-blue.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl6/igt@kms_color@pipe-c-ctm-red-to-blue.html > > * igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen: > - shard-skl: [FAIL][47] ([i915#54]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html > > * igt@kms_cursor_crc@pipe-b-cursor-suspend: > - shard-apl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html > > * igt@kms_cursor_legacy@pipe-c-torture-move: > - shard-hsw: [DMESG-WARN][51] ([i915#128]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-hsw1/igt@kms_cursor_legacy@pipe-c-torture-move.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-hsw4/igt@kms_cursor_legacy@pipe-c-torture-move.html > > * igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: > - shard-apl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl6/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl2/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html > > * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu: > - shard-apl: [DMESG-WARN][55] ([i915#95]) -> [PASS][56] +17 similar issues > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html > > * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt: > - shard-skl: [FAIL][57] ([i915#49]) -> [PASS][58] +1 similar issue > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html > > * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: [FAIL][59] ([fdo#108145] / [i915#265]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html > > * igt@kms_psr@psr2_sprite_render: > - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +2 similar issues > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb3/igt@kms_psr@psr2_sprite_render.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-iclb2/igt@kms_psr@psr2_sprite_render.html > > * igt@kms_setmode@basic: > - shard-apl: [FAIL][63] ([i915#31]) -> [PASS][64] > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl2/igt@kms_setmode@basic.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl1/igt@kms_setmode@basic.html > > * igt@kms_vblank@pipe-a-wait-forked-hang: > - shard-hsw: [INCOMPLETE][65] ([i915#61]) -> [PASS][66] > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-hsw4/igt@kms_vblank@pipe-a-wait-forked-hang.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-hsw8/igt@kms_vblank@pipe-a-wait-forked-hang.html > > > #### Warnings #### > > * igt@i915_pm_rc6_residency@rc6-idle: > - shard-iclb: [WARN][67] ([i915#1515]) -> [FAIL][68] ([i915#1515]) > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html > > * igt@kms_content_protection@atomic: > - shard-kbl: [TIMEOUT][69] ([i915#1319] / [i915#1958]) -> [TIMEOUT][70] ([i915#1319]) +1 similar issue > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl4/igt@kms_content_protection@atomic.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl7/igt@kms_content_protection@atomic.html > - shard-apl: [TIMEOUT][71] ([i915#1319]) -> [FAIL][72] ([fdo#110321] / [fdo#110336]) > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl2/igt@kms_content_protection@atomic.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl1/igt@kms_content_protection@atomic.html > > * igt@kms_content_protection@lic: > - shard-kbl: [DMESG-FAIL][73] ([fdo#110321] / [i915#95]) -> [TIMEOUT][74] ([i915#1319]) > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt@kms_content_protection@lic.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl6/igt@kms_content_protection@lic.html > > * igt@kms_content_protection@srm: > - shard-apl: [DMESG-FAIL][75] ([fdo#110321] / [i915#95]) -> [TIMEOUT][76] ([i915#1319] / [i915#1635]) > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl6/igt@kms_content_protection@srm.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl2/igt@kms_content_protection@srm.html > > * igt@kms_frontbuffer_tracking@fbc-suspend: > - shard-kbl: [DMESG-WARN][77] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][78] ([i915#93] / [i915#95]) > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 > [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 > [i915#1630]: https://gitlab.freedesktop.org/drm/intel/issues/1630 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 > [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8596 -> Patchwork_17899 > > CI-20190529: 20190529 > CI_DRM_8596: ac91b8351ce380da73dbe8b87d1e4f95aa0c4409 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17899: c063779ca55740c59aacc4d6ae5ee0ed9a4488e5 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/index.html > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7a0011e42e00..ab380e6dc674 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -537,6 +537,22 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); val |= intel_psr2_get_tp_time(intel_dp); + if (INTEL_GEN(dev_priv) >= 12) { + /* + * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default + * values from BSpec. In order to setting an optimal power + * consumption, lower than 4k resoluition mode needs to decrese + * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution + * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. + */ + val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; + val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); + val |= TGL_EDP_PSR2_FAST_WAKE(7); + } else if (INTEL_GEN(dev_priv) >= 9) { + val |= EDP_PSR2_IO_BUFFER_WAKE(7); + val |= EDP_PSR2_FAST_WAKE(7); + } + /* * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is * recommending keep this bit unset while PSR2 is enabled. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 814a70945468..4066f67175dc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4511,25 +4511,39 @@ enum { #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ -#define _PSR2_CTL_A 0x60900 -#define _PSR2_CTL_EDP 0x6f900 -#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) -#define EDP_PSR2_ENABLE (1 << 31) -#define EDP_SU_TRACK_ENABLE (1 << 30) -#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ -#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ -#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) -#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) -#define EDP_PSR2_TP2_TIME_500us (0 << 8) -#define EDP_PSR2_TP2_TIME_100us (1 << 8) -#define EDP_PSR2_TP2_TIME_2500us (2 << 8) -#define EDP_PSR2_TP2_TIME_50us (3 << 8) -#define EDP_PSR2_TP2_TIME_MASK (3 << 8) -#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 -#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) -#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) -#define EDP_PSR2_IDLE_FRAME_MASK 0xf -#define EDP_PSR2_IDLE_FRAME_SHIFT 0 +#define _PSR2_CTL_A 0x60900 +#define _PSR2_CTL_EDP 0x6f900 +#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) +#define EDP_PSR2_ENABLE (1 << 31) +#define EDP_SU_TRACK_ENABLE (1 << 30) +#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) +#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) +#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ +#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ +#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) +#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) +#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 +#define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) +#define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 +#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) +#define EDP_PSR2_FAST_WAKE_MAX_LINES 8 +#define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11) +#define EDP_PSR2_FAST_WAKE_MASK (3 << 11) +#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 +#define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10) +#define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) +#define EDP_PSR2_TP2_TIME_500us (0 << 8) +#define EDP_PSR2_TP2_TIME_100us (1 << 8) +#define EDP_PSR2_TP2_TIME_2500us (2 << 8) +#define EDP_PSR2_TP2_TIME_50us (3 << 8) +#define EDP_PSR2_TP2_TIME_MASK (3 << 8) +#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 +#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) +#define EDP_PSR2_IDLE_FRAME_MASK 0xf +#define EDP_PSR2_IDLE_FRAME_SHIFT 0 #define _PSR_EVENT_TRANS_A 0x60848 #define _PSR_EVENT_TRANS_B 0x61848
The IO buffer Wake and Fast Wake bit size and value have been changed from Gen12+. It programs the default value of IO buffer Wake and Fast Wake on Gen12+. It adds definitions of IO buffer Wake and Fast Wake for pre Gen12 and Gen12+. And it aligns PSR2 definition macros. v2: Fix macro definitions. (José) v3: Addressed review comments from José - Add missing default values of IO_BUFFER_WAKE and FAST_WAKE for GEN9+ - Change a style of macro naming in order to use lines as input. - Update Todo comments. v4: Add parentheses to macros to avoid precedence issues. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 16 ++++++++ drivers/gpu/drm/i915/i915_reg.h | 52 +++++++++++++++--------- 2 files changed, 49 insertions(+), 19 deletions(-)