Message ID | 20200605213332.609-1-sibis@codeaurora.org (mailing list archive) |
---|---|
Headers | show |
Series | DDR/L3 Scaling support on SDM845 and SC7180 SoCs | expand |
On 06-06-20, 03:03, Sibi Sankar wrote: > This patch series aims to extend cpu based scaling support to L3/DDR on > SDM845 and SC7180 SoCs. > > Patches [1-2] - Blacklist SDM845 and SC7180 in cpufreq-dt-platdev > Patches [3-5] - Update bw levels based on cpu frequency change > > Based on Viresh's opp-next: > https://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git/log/?h=opp/linux-next > > V6: > * Add global flag to distinguish between voltage update and opp add. > Use the same flag before trying to scale ddr/l3 bw [Viresh] > * Use dev_pm_opp_find_freq_ceil to grab all opps [Viresh] > * Move dev_pm_opp_of_find_icc_paths into probe [Viresh] Picked for 5.9, will push to my branch after rc1 is out.