| Message ID | 20200611223016.259837-13-hskinnemoen@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines | expand |
On 6/12/20 12:30 AM, Havard Skinnemoen wrote: > Change-Id: I88e437cb22a8441e0c0e672dfb57568ac81172d8 > Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> > --- > docs/system/arm/nuvoton.rst | 89 +++++++++++++++++++++++++++++++++++++ > docs/system/target-arm.rst | 1 + > 2 files changed, 90 insertions(+) > create mode 100644 docs/system/arm/nuvoton.rst > > diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst > new file mode 100644 > index 0000000000..1ca34c0051 > --- /dev/null > +++ b/docs/system/arm/nuvoton.rst > @@ -0,0 +1,89 @@ > +Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``) > +===================================================== > + > +The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are > +designed to be used as Baseboard Management Controllers (BMCs) in various > +servers. They all feature one or two ARM Cortex A9 CPU cores, as well as an > +assortment of peripherals targeted for either Enterprise or Data Center / > +Hyperscale applications. The former is a superset of the latter, so NPCM750 has > +all the peripherals of NPCM730 and more. > + > +.. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/ > + > +The NPCM750 SoC has two Cortex A9 cores and is targeted for the Enterprise > +segment. The following machines are based on this chip : > + > +- ``npcm750-evb`` Nuvoton NPCM750 Evaluation board > + > +The NPCM730 SoC has two Cortex A9 cores and is targeted for Data Center and > +Hyperscale applications. The following machines are based on this chip : > + > +- ``quanta-gsj`` Quanta GSJ server BMC > + > +There are also two more SoCs, NPCM710 and NPCM705, which are single-core > +variants of NPCM750 and NPCM730, respectively. These are currently not > +supported by QEMU. > + > +Supported devices > +----------------- > + > + * SMP (Dual Core Cortex-A9) > + * Cortex-A9MPCore built-in peripherals: SCU, GIC, Global Timer, Private Timer > + and Watchdog. > + * SRAM, ROM and DRAM mappings > + * System Global Control Registers (GCR) > + * Clock and reset controller (CLK) > + * Timer controller (TIM) > + * Serial ports (16550-based) > + * DDR4 memory controller (dummy interface indicating memory training is done) > + * OTP controllers (no protection features) > + * Flash Interface Unit (FIU; no protection features) > + > +Missing devices > +--------------- > + > + * GPIO controller > + * LPC/eSPI host-to-BMC interface, including > + > + * Keyboard and mouse controller interface (KBCI) > + * Keyboard Controller Style (KCS) channels > + * BIOS POST code FIFO > + * System Wake-up Control (SWC) > + * Shared memory (SHM) > + * eSPI slave interface > + > + * Ethernet controllers (GMAC and EMC) > + * USB host (USBH) > + * USB device (USBD) > + * SMBus controller (SMBF) > + * Peripheral SPI controller (PSPI) > + * Analog to Digital Converter (ADC) > + * SD/MMC host > + * Random Number Generator (RNG) > + * PECI interface > + * Pulse Width Modulation (PWM) > + * Tachometer > + * PCI and PCIe root complex and bridges > + * VDM and MCTP support > + * Serial I/O expansion > + * LPC/eSPI host > + * Coprocessor > + * Graphics > + * Video capture > + * Encoding compression engine > + * Security features > + > +Boot options > +------------ > + > +The Nuvoton machines can boot from an OpenBMC firmware image, or directly into > +a kernel using the ``-kernel`` option. > + > +Booting a full firmware image requires a Boot ROM specified via the ``-bios`` > +option to QEMU. The firmware image should be attached as an MTD drive. Example : > + > +.. code-block:: bash > + > + $ qemu-system-arm -machine quanta-gsj -nographic \ > + -bios npcm7xx_bootrom.bin \ > + -drive file=image-bmc,if=mtd,bus=0,unit=0,format=raw > diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst > index 1bd477a293..38a9daa9b9 100644 > --- a/docs/system/target-arm.rst > +++ b/docs/system/target-arm.rst > @@ -84,6 +84,7 @@ undocumented; you can get a complete list by running > arm/aspeed > arm/musicpal > arm/nseries > + arm/nuvoton > arm/orangepi > arm/palm > arm/xscale >
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst new file mode 100644 index 0000000000..1ca34c0051 --- /dev/null +++ b/docs/system/arm/nuvoton.rst @@ -0,0 +1,89 @@ +Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``) +===================================================== + +The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are +designed to be used as Baseboard Management Controllers (BMCs) in various +servers. They all feature one or two ARM Cortex A9 CPU cores, as well as an +assortment of peripherals targeted for either Enterprise or Data Center / +Hyperscale applications. The former is a superset of the latter, so NPCM750 has +all the peripherals of NPCM730 and more. + +.. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/ + +The NPCM750 SoC has two Cortex A9 cores and is targeted for the Enterprise +segment. The following machines are based on this chip : + +- ``npcm750-evb`` Nuvoton NPCM750 Evaluation board + +The NPCM730 SoC has two Cortex A9 cores and is targeted for Data Center and +Hyperscale applications. The following machines are based on this chip : + +- ``quanta-gsj`` Quanta GSJ server BMC + +There are also two more SoCs, NPCM710 and NPCM705, which are single-core +variants of NPCM750 and NPCM730, respectively. These are currently not +supported by QEMU. + +Supported devices +----------------- + + * SMP (Dual Core Cortex-A9) + * Cortex-A9MPCore built-in peripherals: SCU, GIC, Global Timer, Private Timer + and Watchdog. + * SRAM, ROM and DRAM mappings + * System Global Control Registers (GCR) + * Clock and reset controller (CLK) + * Timer controller (TIM) + * Serial ports (16550-based) + * DDR4 memory controller (dummy interface indicating memory training is done) + * OTP controllers (no protection features) + * Flash Interface Unit (FIU; no protection features) + +Missing devices +--------------- + + * GPIO controller + * LPC/eSPI host-to-BMC interface, including + + * Keyboard and mouse controller interface (KBCI) + * Keyboard Controller Style (KCS) channels + * BIOS POST code FIFO + * System Wake-up Control (SWC) + * Shared memory (SHM) + * eSPI slave interface + + * Ethernet controllers (GMAC and EMC) + * USB host (USBH) + * USB device (USBD) + * SMBus controller (SMBF) + * Peripheral SPI controller (PSPI) + * Analog to Digital Converter (ADC) + * SD/MMC host + * Random Number Generator (RNG) + * PECI interface + * Pulse Width Modulation (PWM) + * Tachometer + * PCI and PCIe root complex and bridges + * VDM and MCTP support + * Serial I/O expansion + * LPC/eSPI host + * Coprocessor + * Graphics + * Video capture + * Encoding compression engine + * Security features + +Boot options +------------ + +The Nuvoton machines can boot from an OpenBMC firmware image, or directly into +a kernel using the ``-kernel`` option. + +Booting a full firmware image requires a Boot ROM specified via the ``-bios`` +option to QEMU. The firmware image should be attached as an MTD drive. Example : + +.. code-block:: bash + + $ qemu-system-arm -machine quanta-gsj -nographic \ + -bios npcm7xx_bootrom.bin \ + -drive file=image-bmc,if=mtd,bus=0,unit=0,format=raw diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 1bd477a293..38a9daa9b9 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -84,6 +84,7 @@ undocumented; you can get a complete list by running arm/aspeed arm/musicpal arm/nseries + arm/nuvoton arm/orangepi arm/palm arm/xscale
Change-Id: I88e437cb22a8441e0c0e672dfb57568ac81172d8 Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> --- docs/system/arm/nuvoton.rst | 89 +++++++++++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + 2 files changed, 90 insertions(+) create mode 100644 docs/system/arm/nuvoton.rst