| Message ID | 20200626200414.14382-7-jcrouse@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | iommu-arm-smmu: Add auxiliary domains and per-instance pagetables | expand |
On Fri, Jun 26, 2020 at 1:04 PM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > Add support for using per-instance pagetables if all the dependencies are > available. > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > --- > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 43 +++++++++++++++++++++++++++ > drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + > 2 files changed, 44 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index aa53f47b7e8b..95ed2ceac121 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -79,6 +79,34 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, > OUT_RING(ring, upper_32_bits(iova)); > } > > +static void a6xx_set_pagetable(struct msm_gpu *gpu, struct msm_ringbuffer *ring, > + struct msm_file_private *ctx) > +{ > + phys_addr_t ttbr; > + u32 asid; > + > + if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) > + return; > + > + /* Execute the table update */ > + OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); > + OUT_RING(ring, lower_32_bits(ttbr)); > + OUT_RING(ring, (((u64) asid) << 48) | upper_32_bits(ttbr)); > + /* CONTEXTIDR is currently unused */ > + OUT_RING(ring, 0); > + /* CONTEXTBANK is currently unused */ > + OUT_RING(ring, 0); > + > + /* > + * Write the new TTBR0 to the memstore. This is good for debugging. > + */ > + OUT_PKT7(ring, CP_MEM_WRITE, 4); > + OUT_RING(ring, lower_32_bits(rbmemptr(ring, ttbr0))); > + OUT_RING(ring, upper_32_bits(rbmemptr(ring, ttbr0))); > + OUT_RING(ring, lower_32_bits(ttbr)); > + OUT_RING(ring, (((u64) asid) << 48) | upper_32_bits(ttbr)); > +} > + > static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, > struct msm_file_private *ctx) > { > @@ -89,6 +117,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, > struct msm_ringbuffer *ring = submit->ring; > unsigned int i; > > + a6xx_set_pagetable(gpu, ring, ctx); > + > get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, > rbmemptr_stats(ring, index, cpcycles_start)); > > @@ -872,6 +902,18 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) > return (unsigned long)busy_time; > } > > +struct msm_gem_address_space *a6xx_address_space_instance(struct msm_gpu *gpu) > +{ > + struct msm_mmu *mmu; > + > + mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); > + if (IS_ERR(mmu)) > + return msm_gem_address_space_get(gpu->aspace); > + > + return msm_gem_address_space_create(mmu, > + "gpu", 0x100000000ULL, 0x1ffffffffULL); > +} > + > static const struct adreno_gpu_funcs funcs = { > .base = { > .get_param = adreno_get_param, > @@ -895,6 +937,7 @@ static const struct adreno_gpu_funcs funcs = { > .gpu_state_put = a6xx_gpu_state_put, > #endif > .create_address_space = adreno_iommu_create_address_space, > + .address_space_instance = a6xx_address_space_instance, Hmm, maybe instead of .address_space_instance, something like .create_context_address_space? Since like .create_address_space, it is creating an address space.. the difference is that it is a per context/process aspace.. BR, -R > }, > .get_timestamp = a6xx_get_timestamp, > }; > diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h > index 7764373d0ed2..0987d6bf848c 100644 > --- a/drivers/gpu/drm/msm/msm_ringbuffer.h > +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h > @@ -31,6 +31,7 @@ struct msm_rbmemptrs { > volatile uint32_t fence; > > volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT]; > + volatile u64 ttbr0; > }; > > struct msm_ringbuffer { > -- > 2.17.1 >
On Sat, Jun 27, 2020 at 12:56 PM Rob Clark <robdclark@gmail.com> wrote: > > On Fri, Jun 26, 2020 at 1:04 PM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > > > Add support for using per-instance pagetables if all the dependencies are > > available. > > > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > > --- > > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 43 +++++++++++++++++++++++++++ > > drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + > > 2 files changed, 44 insertions(+) > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > index aa53f47b7e8b..95ed2ceac121 100644 > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > @@ -79,6 +79,34 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, > > OUT_RING(ring, upper_32_bits(iova)); > > } > > > > +static void a6xx_set_pagetable(struct msm_gpu *gpu, struct msm_ringbuffer *ring, > > + struct msm_file_private *ctx) > > +{ > > + phys_addr_t ttbr; > > + u32 asid; > > + > > + if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) > > + return; > > + > > + /* Execute the table update */ > > + OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); > > + OUT_RING(ring, lower_32_bits(ttbr)); > > + OUT_RING(ring, (((u64) asid) << 48) | upper_32_bits(ttbr)); > > + /* CONTEXTIDR is currently unused */ > > + OUT_RING(ring, 0); > > + /* CONTEXTBANK is currently unused */ > > + OUT_RING(ring, 0); > > + > > + /* > > + * Write the new TTBR0 to the memstore. This is good for debugging. > > + */ > > + OUT_PKT7(ring, CP_MEM_WRITE, 4); > > + OUT_RING(ring, lower_32_bits(rbmemptr(ring, ttbr0))); > > + OUT_RING(ring, upper_32_bits(rbmemptr(ring, ttbr0))); > > + OUT_RING(ring, lower_32_bits(ttbr)); > > + OUT_RING(ring, (((u64) asid) << 48) | upper_32_bits(ttbr)); > > +} > > + > > static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, > > struct msm_file_private *ctx) > > { > > @@ -89,6 +117,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, > > struct msm_ringbuffer *ring = submit->ring; > > unsigned int i; > > > > + a6xx_set_pagetable(gpu, ring, ctx); > > + > > get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, > > rbmemptr_stats(ring, index, cpcycles_start)); > > > > @@ -872,6 +902,18 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) > > return (unsigned long)busy_time; > > } > > > > +struct msm_gem_address_space *a6xx_address_space_instance(struct msm_gpu *gpu) > > +{ > > + struct msm_mmu *mmu; > > + > > + mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); > > + if (IS_ERR(mmu)) > > + return msm_gem_address_space_get(gpu->aspace); > > + > > + return msm_gem_address_space_create(mmu, > > + "gpu", 0x100000000ULL, 0x1ffffffffULL); > > +} > > + > > static const struct adreno_gpu_funcs funcs = { > > .base = { > > .get_param = adreno_get_param, > > @@ -895,6 +937,7 @@ static const struct adreno_gpu_funcs funcs = { > > .gpu_state_put = a6xx_gpu_state_put, > > #endif > > .create_address_space = adreno_iommu_create_address_space, > > + .address_space_instance = a6xx_address_space_instance, > > Hmm, maybe instead of .address_space_instance, something like > .create_context_address_space? > > Since like .create_address_space, it is creating an address space.. > the difference is that it is a per context/process aspace.. > or maybe just .create_pgtable and return the 'struct msm_mmu' (which is itself starting to become less of a great name).. The only other thing a6xx_address_space_instance() adds is knowing where the split is between the kernel and user pgtables, and I suppose that isn't a thing that would really be changing between gens? BR, -R > BR, > -R > > > }, > > .get_timestamp = a6xx_get_timestamp, > > }; > > diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h > > index 7764373d0ed2..0987d6bf848c 100644 > > --- a/drivers/gpu/drm/msm/msm_ringbuffer.h > > +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h > > @@ -31,6 +31,7 @@ struct msm_rbmemptrs { > > volatile uint32_t fence; > > > > volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT]; > > + volatile u64 ttbr0; > > }; > > > > struct msm_ringbuffer { > > -- > > 2.17.1 > >
On Sat, Jun 27, 2020 at 01:11:14PM -0700, Rob Clark wrote: > On Sat, Jun 27, 2020 at 12:56 PM Rob Clark <robdclark@gmail.com> wrote: > > > > On Fri, Jun 26, 2020 at 1:04 PM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > > > > > Add support for using per-instance pagetables if all the dependencies are > > > available. > > > > > > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> > > > --- > > > > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 43 +++++++++++++++++++++++++++ > > > drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + > > > 2 files changed, 44 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > index aa53f47b7e8b..95ed2ceac121 100644 > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > > @@ -79,6 +79,34 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, > > > OUT_RING(ring, upper_32_bits(iova)); > > > } > > > > > > +static void a6xx_set_pagetable(struct msm_gpu *gpu, struct msm_ringbuffer *ring, > > > + struct msm_file_private *ctx) > > > +{ > > > + phys_addr_t ttbr; > > > + u32 asid; > > > + > > > + if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) > > > + return; > > > + > > > + /* Execute the table update */ > > > + OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); > > > + OUT_RING(ring, lower_32_bits(ttbr)); > > > + OUT_RING(ring, (((u64) asid) << 48) | upper_32_bits(ttbr)); > > > + /* CONTEXTIDR is currently unused */ > > > + OUT_RING(ring, 0); > > > + /* CONTEXTBANK is currently unused */ > > > + OUT_RING(ring, 0); > > > + > > > + /* > > > + * Write the new TTBR0 to the memstore. This is good for debugging. > > > + */ > > > + OUT_PKT7(ring, CP_MEM_WRITE, 4); > > > + OUT_RING(ring, lower_32_bits(rbmemptr(ring, ttbr0))); > > > + OUT_RING(ring, upper_32_bits(rbmemptr(ring, ttbr0))); > > > + OUT_RING(ring, lower_32_bits(ttbr)); > > > + OUT_RING(ring, (((u64) asid) << 48) | upper_32_bits(ttbr)); > > > +} > > > + > > > static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, > > > struct msm_file_private *ctx) > > > { > > > @@ -89,6 +117,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, > > > struct msm_ringbuffer *ring = submit->ring; > > > unsigned int i; > > > > > > + a6xx_set_pagetable(gpu, ring, ctx); > > > + > > > get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, > > > rbmemptr_stats(ring, index, cpcycles_start)); > > > > > > @@ -872,6 +902,18 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) > > > return (unsigned long)busy_time; > > > } > > > > > > +struct msm_gem_address_space *a6xx_address_space_instance(struct msm_gpu *gpu) > > > +{ > > > + struct msm_mmu *mmu; > > > + > > > + mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); > > > + if (IS_ERR(mmu)) > > > + return msm_gem_address_space_get(gpu->aspace); > > > + > > > + return msm_gem_address_space_create(mmu, > > > + "gpu", 0x100000000ULL, 0x1ffffffffULL); > > > +} > > > + > > > static const struct adreno_gpu_funcs funcs = { > > > .base = { > > > .get_param = adreno_get_param, > > > @@ -895,6 +937,7 @@ static const struct adreno_gpu_funcs funcs = { > > > .gpu_state_put = a6xx_gpu_state_put, > > > #endif > > > .create_address_space = adreno_iommu_create_address_space, > > > + .address_space_instance = a6xx_address_space_instance, > > > > Hmm, maybe instead of .address_space_instance, something like > > .create_context_address_space? > > > > Since like .create_address_space, it is creating an address space.. > > the difference is that it is a per context/process aspace.. > > This is a good suggestion. I'm always open to changing function names. > > > or maybe just .create_pgtable and return the 'struct msm_mmu' (which > is itself starting to become less of a great name).. > > The only other thing a6xx_address_space_instance() adds is knowing > where the split is between the kernel and user pgtables, and I suppose > that isn't a thing that would really be changing between gens? In theory the split is determined by the hardware but its been the same for all a5xx/a6xx targets. Jordan > BR, > -R > > > BR, > > -R > > > > > }, > > > .get_timestamp = a6xx_get_timestamp, > > > }; > > > diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h > > > index 7764373d0ed2..0987d6bf848c 100644 > > > --- a/drivers/gpu/drm/msm/msm_ringbuffer.h > > > +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h > > > @@ -31,6 +31,7 @@ struct msm_rbmemptrs { > > > volatile uint32_t fence; > > > > > > volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT]; > > > + volatile u64 ttbr0; > > > }; > > > > > > struct msm_ringbuffer { > > > -- > > > 2.17.1 > > > > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index aa53f47b7e8b..95ed2ceac121 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -79,6 +79,34 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, OUT_RING(ring, upper_32_bits(iova)); } +static void a6xx_set_pagetable(struct msm_gpu *gpu, struct msm_ringbuffer *ring, + struct msm_file_private *ctx) +{ + phys_addr_t ttbr; + u32 asid; + + if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) + return; + + /* Execute the table update */ + OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); + OUT_RING(ring, lower_32_bits(ttbr)); + OUT_RING(ring, (((u64) asid) << 48) | upper_32_bits(ttbr)); + /* CONTEXTIDR is currently unused */ + OUT_RING(ring, 0); + /* CONTEXTBANK is currently unused */ + OUT_RING(ring, 0); + + /* + * Write the new TTBR0 to the memstore. This is good for debugging. + */ + OUT_PKT7(ring, CP_MEM_WRITE, 4); + OUT_RING(ring, lower_32_bits(rbmemptr(ring, ttbr0))); + OUT_RING(ring, upper_32_bits(rbmemptr(ring, ttbr0))); + OUT_RING(ring, lower_32_bits(ttbr)); + OUT_RING(ring, (((u64) asid) << 48) | upper_32_bits(ttbr)); +} + static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, struct msm_file_private *ctx) { @@ -89,6 +117,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, struct msm_ringbuffer *ring = submit->ring; unsigned int i; + a6xx_set_pagetable(gpu, ring, ctx); + get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, rbmemptr_stats(ring, index, cpcycles_start)); @@ -872,6 +902,18 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) return (unsigned long)busy_time; } +struct msm_gem_address_space *a6xx_address_space_instance(struct msm_gpu *gpu) +{ + struct msm_mmu *mmu; + + mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); + if (IS_ERR(mmu)) + return msm_gem_address_space_get(gpu->aspace); + + return msm_gem_address_space_create(mmu, + "gpu", 0x100000000ULL, 0x1ffffffffULL); +} + static const struct adreno_gpu_funcs funcs = { .base = { .get_param = adreno_get_param, @@ -895,6 +937,7 @@ static const struct adreno_gpu_funcs funcs = { .gpu_state_put = a6xx_gpu_state_put, #endif .create_address_space = adreno_iommu_create_address_space, + .address_space_instance = a6xx_address_space_instance, }, .get_timestamp = a6xx_get_timestamp, }; diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h index 7764373d0ed2..0987d6bf848c 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -31,6 +31,7 @@ struct msm_rbmemptrs { volatile uint32_t fence; volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT]; + volatile u64 ttbr0; }; struct msm_ringbuffer {
Add support for using per-instance pagetables if all the dependencies are available. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 43 +++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + 2 files changed, 44 insertions(+)