| Message ID | 20200702103001.233961-5-robert.marko@sartura.hr (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | net: mdio-ipq4019: add Clause 45 and clock support | expand |
> + clock-frequency: > + default: 100000000 IEEE 802.3 says the default should be 2.5MHz. Some PHYs will go faster, but 100MHz seems unlikely! Andrew
On Thu, Jul 2, 2020 at 3:38 PM Andrew Lunn <andrew@lunn.ch> wrote: > > > + clock-frequency: > > + default: 100000000 > > IEEE 802.3 says the default should be 2.5MHz. Some PHYs will go > faster, but 100MHz seems unlikely! This MDIO controller has an internal divider, by default its set for 100MHz clock. In IPQ4019 MDIO clock is not controllable but in IPQ6018 etc it's controllable. That is the only combination I have currently seen used by Qualcomm. > > Andrew
On 7/2/2020 12:18 PM, Robert Marko wrote: > On Thu, Jul 2, 2020 at 3:38 PM Andrew Lunn <andrew@lunn.ch> wrote: >> >>> + clock-frequency: >>> + default: 100000000 >> >> IEEE 802.3 says the default should be 2.5MHz. Some PHYs will go >> faster, but 100MHz seems unlikely! > This MDIO controller has an internal divider, by default its set for > 100MHz clock. > In IPQ4019 MDIO clock is not controllable but in IPQ6018 etc it's controllable. > That is the only combination I have currently seen used by Qualcomm. Not sure I understand here, the 'clock-frequency' is supposed to denote the MDIO bus output clock frequency, that is the frequency at which all MDIO devices are going to operate at. Is this 100MHz a clock that feeds into the MDIO block and get internally divided by a programmable register to obtain an output MDIO clock?
On Thu, Jul 2, 2020 at 10:04 PM Florian Fainelli <f.fainelli@gmail.com> wrote: > > > > On 7/2/2020 12:18 PM, Robert Marko wrote: > > On Thu, Jul 2, 2020 at 3:38 PM Andrew Lunn <andrew@lunn.ch> wrote: > >> > >>> + clock-frequency: > >>> + default: 100000000 > >> > >> IEEE 802.3 says the default should be 2.5MHz. Some PHYs will go > >> faster, but 100MHz seems unlikely! > > This MDIO controller has an internal divider, by default its set for > > 100MHz clock. > > In IPQ4019 MDIO clock is not controllable but in IPQ6018 etc it's controllable. > > That is the only combination I have currently seen used by Qualcomm. > > Not sure I understand here, the 'clock-frequency' is supposed to denote > the MDIO bus output clock frequency, that is the frequency at which all > MDIO devices are going to operate at. Is this 100MHz a clock that feeds > into the MDIO block and get internally divided by a programmable > register to obtain an output MDIO clock? Yes, in this case that 100MHz comes from the GCC clock controller and is then internally divided by the MDIO. I do not know what is the actual output MDIO bus frequency as datasheet only denotes that MDC divide bits in the mode register are set for 100MHz incoming clock. > -- > Florian
diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml index 13555a89975f..06b4eedb4370 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml @@ -25,6 +25,17 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 1 + + clock-names: + items: + - const: mdio_ahb + maxItems: 1 + + clock-frequency: + default: 100000000 + required: - compatible - reg
This adds the necessary bindings for SoC-s that have a separate MDIO clock. Signed-off-by: Robert Marko <robert.marko@sartura.hr> --- .../devicetree/bindings/net/qcom,ipq4019-mdio.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+)