| Message ID | 20200622075956.171058-5-bjorn.andersson@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hwspinlock: qcom: Allow dropping the intermediate TCSR mutex syscon | expand |
On Mon, 22 Jun 2020 at 11:00, Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > > Now that we don't need the intermediate syscon to represent the TCSR > mutexes, update the dts to describe the TCSR mutex directly under /soc. > > The change also fixes the sort order of the nodes. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On Mon, Jun 22, 2020 at 12:59:56AM -0700, Bjorn Andersson wrote: > Now that we don't need the intermediate syscon to represent the TCSR > mutexes, update the dts to describe the TCSR mutex directly under /soc. > > The change also fixes the sort order of the nodes. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > --- > > Changs since v1: > - Adjusted sort order of the nodes > > arch/arm64/boot/dts/qcom/sm8250.dtsi | 17 ++++++----------- > 1 file changed, 6 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index 7050adba7995..67a1b6f3301b 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -144,12 +144,6 @@ scm: scm { > }; > }; > > - tcsr_mutex: hwlock { > - compatible = "qcom,tcsr-mutex"; > - syscon = <&tcsr_mutex_regs 0 0x1000>; > - #hwlock-cells = <1>; > - }; > - > memory@80000000 { > device_type = "memory"; > /* We expect the bootloader to fill in the size */ > @@ -376,6 +370,12 @@ ufs_mem_phy_lanes: lanes@1d87400 { > }; > }; > > + tcsr_mutex: hwlock@1f40000 { > + compatible = "qcom,tcsr-mutex"; > + reg = <0x0 0x01f40000 0x0 0x40000>; > + #hwlock-cells = <1>; > + }; > + > intc: interrupt-controller@17a00000 { > compatible = "arm,gic-v3"; > #interrupt-cells = <3>; > @@ -486,11 +486,6 @@ rpmhpd_opp_turbo_l1: opp10 { > }; > }; > > - tcsr_mutex_regs: syscon@1f40000 { > - compatible = "syscon"; > - reg = <0x0 0x01f40000 0x0 0x40000>; > - }; > - > timer@17c20000 { > #address-cells = <2>; > #size-cells = <2>; > -- > 2.26.2 >
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7050adba7995..67a1b6f3301b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -144,12 +144,6 @@ scm: scm { }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -376,6 +370,12 @@ ufs_mem_phy_lanes: lanes@1d87400 { }; }; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -486,11 +486,6 @@ rpmhpd_opp_turbo_l1: opp10 { }; }; - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x0 0x01f40000 0x0 0x40000>; - }; - timer@17c20000 { #address-cells = <2>; #size-cells = <2>;
Now that we don't need the intermediate syscon to represent the TCSR mutexes, update the dts to describe the TCSR mutex directly under /soc. The change also fixes the sort order of the nodes. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- Changs since v1: - Adjusted sort order of the nodes arch/arm64/boot/dts/qcom/sm8250.dtsi | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-)